#PBC layout question for anyone who knows more than I do about the subject (essentially everyone)...
Is it ok to put decoupling caps under the #iCE40 package (like the 3 red ones in the image) or am I better off keeping them on the same side as the IC (like the blue ones)? I only have 2 layers to play with and lots of routing on one (still to do on blue), so plan to use the other as (mostly) ground plane and power anyway.
@jeffpc Having them on the other side looks fine to me, as long as they don't split up your ground plane too badly and you keep ground loops in mind. You add a bit of inductance with those vias, but since that chip is in a massive LQFP with long (~10mm) internal leads anyway, that 1.5mm should hardly matter. To keep inductance as low as possible, I'd maybe consider using wider traces where possible (e.g. from via to cap), and making the vias wider where space is available.
Add comment