"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
Current status: proof reading the schematics. I’m following every connection and using highlighter pens to mark where I’ve been. And doing the same to my schematics. The assortment of colours helps to stop me getting muddled.
Thus probably counts as tedious but my brain enjoys this kind of task.
Adding a page of spare units, based off the table on the original schematics, but the design checker doesn't like it.
So, the original is hard to read, and I've not double checked what I've copied, but it clearly shows Z95 with some spare units. But Z95 is one of the RAM chips making up the stack. So this table is definitely error prone.
Adding footprints. No difficulty here. There's only 8 different footprints across the board: 3 for connectors; 2 for capacitors; 1 for resistors; and 2 for chips.
This was the early days of 74 series logic so only 14- and 16-pin packages in use.
Now this is the dictionary definition of tedium. An entire page of power units for the logic gates.
Gaps are for chips with power connections on the main symbol. Not, BTW, the same as chips containing a single unit - there are several 8-input gates with one unit per chip but those still have a separate power unit.
I've copied the Decoder PCB to get the edges of the Processor PCB. I'm using a print out of the decoder PCB and the long edge dimension of the decoder board to work out the scale of the print out.
I can then measure and scale up from the print out.
I'll keep the old decoder components and silk screen for the moment to reuse dimensions and design standards.
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.
The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.