@azonenberg@ioc.exchange
@azonenberg@ioc.exchange avatar

azonenberg

@azonenberg@ioc.exchange

Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"

Toots searchable on tootfinder.

This profile is from a federated server and may be incomplete. Browse more on the original instance.

azonenberg, to random
@azonenberg@ioc.exchange avatar

New ebay score!

No idea what condition it's in, need to find or make a breakout for it.

Anybody know of a readily available commercial or OSH breakout before I design one of my own?

RichiH, to random
@RichiH@chaos.social avatar

"lots of travel" is the realization that your shower habits at home have fully adapted to how North American showers work.

I.e. leaving the water running while getting out of the water stream to soap up as you're used to never touching the controls lest you make the water ice cold or scalding hot. And that "water on/off" is directly tied to temperature control.

azonenberg,
@azonenberg@ioc.exchange avatar

@RichiH The single control knob is common, but not exclusive. Some older American showers (most commonly those attached to tubs) have two knobs for independently adjusting hot and cold just like a sink. These seem to have fallen out of favor.

I've also seen coaxial levers with a big outer arm for water flow rate and a smaller mix ratio knob at the center for adjusting temperature. This is my favorite and I'm hoping to find one when I renovate my falling-apart 1970s bathroom.

azonenberg,
@azonenberg@ioc.exchange avatar

@RichiH Yep, all of mine have a separate output selector as well since they're tub+shower setups.

But they're a somewhat annoying configuration with one knob that you pull out to turn water on and rotate to adjust temperature.

azonenberg, to random
@azonenberg@ioc.exchange avatar

This is clearly not meant to be disassembled. Anyone have ideas? I assume the textured side has to be some kind of nut?

(It's fried and constantly trips with no load giving the "internal fault" LED code, curious what's inside and if there's any visible damage)

Rounded bolt head that doesn't look like a good entry vector

azonenberg,
@azonenberg@ioc.exchange avatar

@f4grx Not planning to put it back together, I just wanted to avoid collateral damage to anything I might want to look at inside.

Guess I'm drilling.

foone, to random
@foone@digipres.club avatar

Fun bug: my wife and I were playing Wheel of Fortune on the switch. We each created female characters, but the game crashed while spinning the wheel. Fortunately it saves your mid-game progress, except when we resumed playing, my wife's character was now a man.

She got transed by a crash!

azonenberg,
@azonenberg@ioc.exchange avatar

@foone That's the weirdest isekai I've ever heard of.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Went to a festival downtown with wife and kid earlier today. Had a bunch of carnival food but she was too small for all the rides so we went back after a bit.

Wife commented on how we basically just stuffed our faces and left and I responded "Yeah, like a pacifistic panda!"

She was confused until I explained "Yeah... Eats, shoots, and leaves... Minus the shooting part!"

18+ nota, to random
@nota@chaos.social avatar

wenn die DDR so gut war wo ist die QDR

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota So-called QDR RAM is actually two DDR ports, one for reads and one for writes (in older generations) or two bidirectional (for newer). But normally they're sharing one common clock not 90 deg phased.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota Not really. QDR-II+ (only family I have specific experience with) is one parallel command/address bus at single rate, alternating issuing requests to the read and write data buses (BL=4, DDR).

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota Burst length 4.

So at T=0 you send a write enable and write address, then at T=1/1.5/2/2.5 you send write data.

At T=1 you send a read enable and read address, then at T=2/2.5/3/3.5 you get read data (simplifying a bit since there's usually some read latency, but you get the idea).

Then at T=2 you can issue another write, and so on.

There's no hard requirement that you have a strict even/odd alternation of reads and writes, but it makes controller design simple and lets you saturate both data buses so it's the logical way to do it.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota It's more like regular SPI than QSPI in that it's full duplex with separate read and write data buses active simultaneously (just that each bus is 18/36 bits wide).

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota Correct. It's poorly named, I consider it dual port DDR.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @nota I have never seen it in the wild.

lethalbit, to random
@lethalbit@chaos.social avatar

Has anyone used OpenEMS to calculate trace impedance profiles from a PCB stackup before?

I'm looking around for decent and fast 2d field solvers for that kinda thing but outside of like 4 HUGE and expensive software suites there really isn't anything for the at home catgirl

azonenberg,
@azonenberg@ioc.exchange avatar

@lethalbit + @niconiconi

In the meantime, if you can't get anything working I'll gladly crunch some numbers for you on my Sonnet seat.

azonenberg,
@azonenberg@ioc.exchange avatar

@lethalbit Lite is fine for simple microstrip and stripline geometry but the thin metal model breaks down for, among other things, tightly coupled CPWG.

mwk, to random
@mwk@donotsta.re avatar

looking for recommendations of schematic drawing software; specifically, I want to draw the insides of an FPGA logic block for documentation purposes (I'm reversing FPGAs and want to have better documentation than https://prjunnamed.github.io/prjcombine/xc2v/clb-xc3s.html )

requirements:

  • I won't hate it too much after drawing a lot of them
  • has layers or something, so I can easily draw a base schematic and then create a dozen distinct highlighted versions
  • the result can be included in docs that will work in both light mode and dark mode
azonenberg,
@azonenberg@ioc.exchange avatar

@mwk To date I haven't found anything better than inkscape or dia. Good luck and let me know if you find anything...

whitequark, to random
@whitequark@mastodon.social avatar

software engineering really gets a different vibe if changing a single character and rebuilding takes about half a hour

android has prepared me for this

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark And this isn't an FPGA system?

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark You don't work for $dayjobclient do you? :p

We have one customer that has an embedded Linux device with a single "God binary" that has idk how many dozens of services compiled into a single executable. IDA takes a couple of hours to fully load it.

It makes systemd look like a textbook example of modularity.

dlharmon, to random
@dlharmon@chaos.social avatar

Fins milled off the heatsink revealing surprise heatpipes. Not sure to keep them or mill through, put a copper block on top of the FPGA.

Glasgow jtag-pinout didn't find any JTAG ports in the 11 pins that had diodes to 1.8 V. The board has blind vias for JTAG on the FPGA so tracing will be hard. The management controller can take over the JTAG, may be doing so. More to trace.

azonenberg,
@azonenberg@ioc.exchange avatar

@dlharmon 135 amps on vccint?

(reaches for tig welder)

azonenberg,
@azonenberg@ioc.exchange avatar

@dlharmon What do you know about the Alveo U30?

azonenberg,
@azonenberg@ioc.exchange avatar

@dlharmon Oh interesting, so the U30 is just a transcoding accelerator and nothing else?

azonenberg,
@azonenberg@ioc.exchange avatar

@dlharmon What does that idcode come back to? Is it literally the virtex?

azonenberg, to random
@azonenberg@ioc.exchange avatar

I think this is next level cursed. But it actually worked.

azonenberg,
@azonenberg@ioc.exchange avatar

@jaseg The cursed bit is that the stm32 OCTOSPI has prefetching and caching you can't disable (since it's meant for XIP on SPI flash), and a bunch of annoying errata.

azonenberg,
@azonenberg@ioc.exchange avatar

@jaseg (also I looked into the FMC and it seemed harder to use for this purpose than the OCTOSPI, although at some point I may spin a test board and try it out if I have enough free IOs.)

azonenberg, to random
@azonenberg@ioc.exchange avatar

New thread on my big ongoing embedded project since the other one was getting too big.

To recap, this is a pilot project for a bunch of my future open hardware T&M and networking projects, validating a common platform that a lot of the future stuff is going to run on.

The primary problem it's trying to address is that I have a lot of instrumentation with trigger in/out ports, sometimes at different voltage levels, and I don't always have the same instrument sourcing the trigger every time.

So rather than moving around cables all the time and adding splitters, attenuators, amplifiers, etc. to the trigger signals I decided to make a dedicated device using an old XC7K70T-2FBG484 I had lying around.

Of course, as with any project, there was feature creep.

I'm standardizing on +48V DC for powering all of my future projects as it's high enough to move a lot of power but low enough to be mostly safe to work around live. So I needed to design and validate an intermediate bus converter to bring the 48 down to something like 12 for the rest of the system to use.

The FPGA has four 10G transceiver pairs on it. I used one for 10GbE (not that I need the bandwidth, but I was low on RJ45 ports on this bench and had some free SFP drops) and the rest are hooked up to front panel SMA ports (awaiting cables to go from PCB to panel) to generate PRBSes for instrument deskew.

Since I'm pinning out the transceivers and am planning to build a BERT eventually, I added BERT functionality to the firmware as well (still need to finish a few things but it's mostly usable now).

And since I have transceivers and access to all of the scope triggers, it would be dumb not to build a CDR trigger mode as well. That's in progress.

azonenberg,
@azonenberg@ioc.exchange avatar

Memory mapped writes ended up being a very deep rabbit hole and I stumbled into more silicon bugs/quirks. For now I'm using peripheral mode for writes, but in a cleaner fashion (passing the SFR field directly as an argument vs computing offsets manually), while memory mapping reads.

This should work just fine.

Only three more peripherals to convert over (front panel SPI, SERDES low speed IO, SERDES DRP) and then this whole massive refactoring will be done and I can get back to feature development.

  • All
  • Subscribed
  • Moderated
  • Favorites
  • •
  • megavids
  • InstantRegret
  • rosin
  • modclub
  • Youngstown
  • khanakhh
  • Durango
  • slotface
  • mdbf
  • cubers
  • GTA5RPClips
  • kavyap
  • DreamBathrooms
  • ngwrru68w68
  • JUstTest
  • magazineikmin
  • osvaldo12
  • tester
  • tacticalgear
  • ethstaker
  • Leos
  • thenastyranch
  • everett
  • normalnudes
  • anitta
  • provamag3
  • cisconetworking
  • lostlight
  • All magazines
    •