@dlharmon@chaos.social avatar

dlharmon

@dlharmon@chaos.social

RF and FPGA nerd.

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whitequark, to random
@whitequark@mastodon.social avatar

HDL people: have you ever used DDR buffers in a module that used a negedge clock as its primary clock?

dlharmon,
@dlharmon@chaos.social avatar

@whitequark no

dlharmon,
@dlharmon@chaos.social avatar

@whitequark It's something I'd avoid if at all possible but it's possible there's some odd corner case where it might make sense.

dlharmon, to random
@dlharmon@chaos.social avatar

Fins milled off the heatsink revealing surprise heatpipes. Not sure to keep them or mill through, put a copper block on top of the FPGA.

Glasgow jtag-pinout didn't find any JTAG ports in the 11 pins that had diodes to 1.8 V. The board has blind vias for JTAG on the FPGA so tracing will be hard. The management controller can take over the JTAG, may be doing so. More to trace.

dlharmon,
@dlharmon@chaos.social avatar

@whitequark This is the first time I've really used it. I think it will be a handy tool especially for situations like this.

dlharmon,
@dlharmon@chaos.social avatar

I'm pretty confident I can figure this thing out but there's the temptation to desolder, reball and make a less annoying board for this part. All it needs is power, configuration, clock a few QSFP28s. Power supplies are undersized (60 A VCCINT, 4A MGTAVTT, VCCHBM 8 A limiting to 200 GB/s.)

The chip is a rebadged XCVU35P-2FSVH2104E ($60k at Digikey) which has 8 GB of HBM2 good for > 400 GB/s if you provide sufficient power, 872k LUT6. It's supported in free download Vivado.

dlharmon,
@dlharmon@chaos.social avatar

"All it needs is power ..."

Power would be a serious job. I'd want to achieve the 135 A package power limit on VCCINT plus 20 A of 1.2 V to the HBM.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg AMD doesn't support programming it with Vivado. "User does not have access to these resources on the Alveo U30 card." Would definitely take more hacking. There's no 460k LUT6 part in the US+ lineup, the hard H.264 only exists officially in ZU*EV so it could be a non catalog chip.

dlharmon,
@dlharmon@chaos.social avatar

@gsuberland Interesting. I had no idea that was a thing.

I'd likely go with a TI multiphase controller and their DrMOS modules. Should be about $50 total for the 3-4 phases needed and controller. Not that awful to lay out with how integrated things are these days.

dlharmon,
@dlharmon@chaos.social avatar

Four of the 1.8 V lines in the debug header trace to logic level translators in the vicinity of the management controller. I suspect they are the JTAG, have determined the microcontroller is indeed driving through them as ~OE is 0 V.

Also found the JTAG for the microcontroller. Not planning to do anything with that for now as I don't want to deal with learning MSP432 details. Blowing away the annoying management firmware, replacing it with a simple power sequencer would be nice.

dlharmon,
@dlharmon@chaos.social avatar

Got it. Traced ~OE to Q26 NMOS drain, gate goes to pin 10, is pulled high with a resistor. Ground pin 10 to release JTAG from the translators. Easy enough. I'll try a bitstream tomorrow, expect it to just work.

IDCODE=0x14b77093

Pins
2 TMS
4 TCK
6 TDO
8 TDI
7, 17, 23 GND
1, 29, 30 1.8 V
12 UC TMS (3.3 V)
14 UC TCK
16 UC TDO
18 UC TDI

There are two UARTs to the debug header documented in the contstraints file, I'll put a different frequency on each, figure them out.

Glasgow is really neat.

dlharmon, to random
@dlharmon@chaos.social avatar

Got the Alveo U50, planning to modify it, not sure how much. Definitely cooling as it requires extreme air pressure like in a server.

dlharmon,
@dlharmon@chaos.social avatar

Interesting decoupling with 3 terminal capacitors under the FPGA.

azonenberg, to random
@azonenberg@ioc.exchange avatar

@dlharmon You've done bare metal Zynq-7 stuff right?

Do you have any kind of blog or resources to talk about how to set up an extreme minimalist no-OS bare metal Zynq firmware?

Ideally I'd like just a single source file (not generated by vivado, something I can actually write from scratch) that I can just build with arm-none-eabi-g++, put on a SD card (zynq doesn't allow you to jtag binaries to the PS right?), and then boot up and give me some sign of life by poking a GPIO SFR or something.

Ultimately my goal is to experiment with some truly cursed things that are likely incompatible with all of the generated wrappers, petalinux, etc.

Things like having PL be a CoreSight APB bus master that can poke debug registers on the A9s.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg I've not finished that post but here's a draft. Life has gotten busy. http://harmoninstruments.com/posts/zucmdline.html

If you want IO muxes, memory controller, etc set up, you will need to at least build and link with the ps7_init.{c,h} generated by Vivado. If you don't want that, single file should be doable. Bootgen will take an ELF.

It's possible to directly instantiate the PS7 block in RTL but probably makes more sense to make a simple block design (and script that) as detailed in the post.

dlharmon,
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@azonenberg I should also add XC7Z is much simpler than XCZU in that post but most applies. No CSU and PMU on XC7, bootrom runs on the A9 cores unlike XCZU where the first instruction run on the ARM cores is user code.

lethalbit, to random
@lethalbit@chaos.social avatar

It sure would be cool if I could get a Keithley 2400 for under 3K T~T

dlharmon,
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@lethalbit I looked up the used value of a few things I have and it's absurd how much more expensive they are now than when I bought them. I paid $1600 for my 2400 in 2020 just before prices shot up. New stuff is starting to look like a better value.

gsuberland, to random
@gsuberland@chaos.social avatar

installed Win11 on an old laptop and Rufus prompted me to autopatch the installer to remove the Microsoft account and TPM requirements when I wrote the ISO to USB. cool feature. made it a lot less annoying to set up.

dlharmon,
@dlharmon@chaos.social avatar

@gsuberland Any suggestion on which debloater to use? Might be nice to clean up my Windows machine.

ktemkin, to random
@ktemkin@chaos.social avatar

eight and a half hours of client work later and I’m supposed to be able to do the things on my personal todo list, now?

how does anyone keep up with this? >.>

dlharmon,
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@ktemkin I definitely can't sustain that, consider 80 hours billed a really good month.

azonenberg, to random
@azonenberg@ioc.exchange avatar

@dlharmon If I'm interpreting the 802.3 table 80-8 constraints correctly, 40/100G have absolutely huge skew tolerances (43 ns per lane at SP2 including a 1ns budget for PCB trace skew).

So there's essentially no reason whatsoever to try to match pair-to-pair delay from FPGA to a QSFP28, right? All that matters is skew within each diffpair.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg That's what lane alignment markers are for. All you'd be doing by trying to match inter pair skew would be to add loss, hurt signal integrity. I see so much unnecessary inter pair skew matching on things sent to me for design review in multi-lane embedded clock interfaces, strongly prefer it not be there unless actually required by the spec.

gsuberland, to random
@gsuberland@chaos.social avatar

anyone know if there's a way to directly link to a part (or, ideally, a full set of selections and params) in Samsung's MLCC tool?

https://weblib.samsungsem.com/mlcc/mlcc-ec.do

as it stands I have to link folks to the tool and tell them what parts to select and what parameters to set. would be much easier to share a link.

dlharmon,
@dlharmon@chaos.social avatar

@gsuberland https://product.samsungsem.com/mlcc/CL21A476MQYNNN.do or https://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL21A476MQYNNN
Their website is very broken on Firefox, editing the part number in the link works, might need to strip the last character from the part number.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Is there such a thing as a cost optimized "discharge-only" RF terminator?

Basically, something that you use for discharging ESD from cables and is built to tight mechanical tolerances on the mating interface so as to not risk damage to expensive connectors, but need not be optimized for good return loss out to mm-wave frequencies etc.

@g4dbn @ftg @dlharmon

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg I don't worry too much about that one. How about a connector saver adapter with a cheap terminator? I did make some calibration open/short transfer standards out of field replaceable connectors attached to a copper block. Short had a post to fit the center pin, open a hole.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg I was thinking basic $10 SMA terminator, adapter to 2.92 or SMPM. The adapters aren't cheap but are far cheaper than proper terminators.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg I had in mind something more like a $40 Mini-Circuits KF-SF50+. If you want cheap, you can make a PCB with a connector and resistor. Hirose HK-R-SR2-1 is about $25, good quality, would work well for that.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Does anybody (maybe @dlharmon, @ftg, or @g4dbn) know why so many RF cables are blue?

I thought FEP was a Teflon-like material that was white in the natural state, so I don't think the jacket just happens to be blue. Is it some kind of industry convention for coaxial cables?

I mean sure, there's other colors - semirigid or hand formable are often unjacketed tin plated copper or aluminum, ultra cheap stuff like RG316 is usually a tan color, and the ultra high end stuff like Gore PhaseFlex has a nylon braid shell that I've seen in purple and green, as well as blue.

But pretty much any flexible cable I've bought from Koaxis, Mini-Circuits, SV Microwave, etc. is that same shade of blue, or a slightly translucent lighter blue you can see the shield braid through. So is most Sucoflex.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg I have a handful of cables (Astrolab Steelflex) with clear FEP, another with a translucent purple FEP jacket (Florida RF Lab-Flex 200, not a good cable). There's no real need for a fluorocarbon jacket in most applications but it seems really common. No idea why so many are shades of blue.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Assembling the trigger crossbar board over lunch.

Not thrilled with the paste print quality, very inconsistent. the top left corner was way too thick as the board flexed during printing, the middle BGA skipped some pads, and the WLCSP in the bottom right was near perfect.

These big boards bend too much in my paste fixture, I need to find a way to prevent that before I do any more boards of this scale.

dlharmon,
@dlharmon@chaos.social avatar

@azonenberg Looking at what you posted, the biggest difference is I'm writing 0x300 to 0x3D prior to ES_VERT/HORZ_OFFSET, then 0x301 to 0x3D after to trigger. Bit 8 ES_EYE_SCAN_EN is reserved, set to 1. Terrible poorly documented but working code here: https://gitlab.com/harmoninstruments/ethernet-acquisition/-/blob/main/python/eyescan.py?ref_type=heads

dlharmon, to random
@dlharmon@chaos.social avatar

Put a new clock battery in the R&S FSQ 26. Should have done that long ago, thankfully no leakage and just a CR2032. This is about 20 years old, likely all the serious RF is chip and wire hybrid. All boards except the optional wideband digitizer appear to be plain FR4. I'd be curious to see more but it's too old and fragile to risk taking apart anything I don't have to.

dlharmon,
@dlharmon@chaos.social avatar

@gsuberland They seem reliable, my main concerns would be the power supply, embedded PC, electrolytic caps which it has a few of outside the power supply. I do have an image of the hard drive in case that goes. The YIG oscillators and filters fail on the Agilents, hopefully R&S is better about those.

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