@0h00000000@ioc.exchange avatar

0h00000000

@0h00000000@ioc.exchange

All things embedded, data, science.

This profile is from a federated server and may be incomplete. Browse more on the original instance.

azonenberg, to random
@azonenberg@ioc.exchange avatar

My dream laptop:

  • Form factor of a late 90s / early 2000s (1.5-2" thick, 15" screen size or so) laptop. None of this thin-and-light nonsense.
  • Sunlight readable display capable of being used in reflective (backlight off) mode for reduced power
  • Optional cellular modem module
  • Two (or more) externally accessible, hot-swappable 100Wh batteries with power ORing. If you're going on a plane you can take some of the batteries out to make the FAA happy. But if I'm on the road I want the option to have several batteries and swap them without needing to be plugged in or shut down. The goal is to support multiple days of off-grid usage with no charging access.
  • 1000baseT and 10G SFP+ Ethernet ports
  • Lots of USB A and C ports. 5-10, at least, spread across several roots for improved bandwidth
  • Modular, repairable, upgradeable design so I can e.g. swap out the CPU board when it becomes obsolete but keep all of the peripherals and chassis
0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg This looks interesting - they make some sleek analyzers up to 110GHz, but now adding an Intel based tablet:
https://x.com/Aaronia_AG/status/1788106309394739262

azonenberg, to random
@azonenberg@ioc.exchange avatar

How crazy/horrible/stupid would it be to write a single-pass streaming parser for ELF as part of a firmware updater?

More specifically, you're given a chance to look at each byte of data once. You can either write it to flash immediately, update some local variables (like "offset of .text"), or ignore it.

But once you've seen a given part of the file, you can't rewind and look at it again later (since I'm flashing an image that might be larger than available RAM).

How likely is this to fail in practice? I'm not asking if one of the POC||GTFO editors could craft an ELF that would break this, I'm sure they could. But if I control the linker script generating the file, and have the parser simply refuse to process any file that doesn't play by my rules, am I probably OK?

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg For my updates, I have the crypto accelerators on STM32L4+, and I have server generate a SHA hash and send it with file, and I have STM32L4+ generate a SHA hash as it downloads it and verity before rebooting target. I don't think CRC is very reliable for larger data.

azonenberg, to random
@azonenberg@ioc.exchange avatar

New thread on my big ongoing embedded project since the other one was getting too big.

To recap, this is a pilot project for a bunch of my future open hardware T&M and networking projects, validating a common platform that a lot of the future stuff is going to run on.

The primary problem it's trying to address is that I have a lot of instrumentation with trigger in/out ports, sometimes at different voltage levels, and I don't always have the same instrument sourcing the trigger every time.

So rather than moving around cables all the time and adding splitters, attenuators, amplifiers, etc. to the trigger signals I decided to make a dedicated device using an old XC7K70T-2FBG484 I had lying around.

Of course, as with any project, there was feature creep.

I'm standardizing on +48V DC for powering all of my future projects as it's high enough to move a lot of power but low enough to be mostly safe to work around live. So I needed to design and validate an intermediate bus converter to bring the 48 down to something like 12 for the rest of the system to use.

The FPGA has four 10G transceiver pairs on it. I used one for 10GbE (not that I need the bandwidth, but I was low on RJ45 ports on this bench and had some free SFP drops) and the rest are hooked up to front panel SMA ports (awaiting cables to go from PCB to panel) to generate PRBSes for instrument deskew.

Since I'm pinning out the transceivers and am planning to build a BERT eventually, I added BERT functionality to the firmware as well (still need to finish a few things but it's mostly usable now).

And since I have transceivers and access to all of the scope triggers, it would be dumb not to build a CDR trigger mode as well. That's in progress.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg ST products have a built in bootloader over UART/I2c, if you have right pins connected to your host controller you can use it to flash slave MCU. Or you could make a tiny bootloader and store in first page of flash and never overwrite it.
https://www.st.com/resource/en/application_note/an2606-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.pdf

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Is this OTA for STM32? Do you have dual bank flash on it? I have some code for an L4+ that does OTA.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Yeah, the l4+ has 2MB flash that can be configured as 1MB dual bank with an option bit to select which bank to boot from on reboot, and both banks can be aliased to 0x8000000. I download fresh code into other bank, and hash it and compare with provided hash. That 1MB is divided up with image L4+, and image for ice40 FPGA and image for a SILabs wifi chip. I'll eventually move those images to eMMC at some point.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Oh yeah, I saw this processor/DAC/ADC and thought you might be interested in checking it out, 2x1gsps ADC, 4x500msps ADC, 2x500msps DAC, 6x VSPA vector accel, 6x e200 cores, PCIe. Interesting beast.
https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-access-la12xx-programmable-baseband-processor:LA12xx

azonenberg, to random
@azonenberg@ioc.exchange avatar

Anybody know the typical flow rate (in SCCM or similar volume flow units) and discharge pressure for duster gas cans?

Looking at replacing my current HFO-1234ze cans with N2 for most applications for cost/environmental reasons but trying to figure out how much I'll actually go through and what size regulator I should get (the one I currently have on my N2 tank is meant for very low volume inerting and tops out at 30psi which is likely too low).

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg I use a 20oz CO2 tank for feeding my solder dispenser - lasts a lot longer than N2. I just refill at local paintball shop. II use this regulator:
https://powertank.com/collections/regulators/products/reg-4012c

azonenberg, to random
@azonenberg@ioc.exchange avatar

Dream MCU wishlist item 732: Simple, high-speed serial protocol for fast memory mapped point-to-point IO.

Basically "PCIe lite". 8b/10b coded ~1 Gbps full duplex LVDS with packetized memory read/write requests bridged directly to AHB on the MCU side.

But no PnP enumeration, no device addressing, no request reordering, none of the other complexity of full PCIe. Something you can hang off a Cortex-M7 and use for interfacing to a lower end FPGA faster than QSPI.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg ST has a 8/16 bit PSSI that shares the DCMI interface on some MCU's. I use it to grab 8 bit data from an ice40, and I send commands over SPI. No reason you couldn't do it all on the PSSI port. Lots of traces though.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg What about MIPI? I think I read something about sending commands, and using virtual channels. NXP has a M7 with CSI, and ST has the N6 with CSI whenever its released in 100 years or whatever.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Assembling the trigger crossbar board over lunch.

Not thrilled with the paste print quality, very inconsistent. the top left corner was way too thick as the board flexed during printing, the middle BGA skipped some pads, and the WLCSP in the bottom right was near perfect.

These big boards bend too much in my paste fixture, I need to find a way to prevent that before I do any more boards of this scale.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Sometimes I solder caps on top of caps for debugging. Might be an option.

azonenberg, to random
@azonenberg@ioc.exchange avatar

So this is interesting and annoying.

I've been having intermittent breaker trips on circuit in my lab. The receptacles in this circuit are mostly behind cabinets, the only one in use powers an LED strip in my components cabinet. The last time the breaker popped I unplugged the LED strip (leaving the circuit, in theory, completely unloaded) and a few days later when I checked the panel again it had tripped.

Today I had a bit of downtime and decided to investigate. With the breaker locked out in the panel and the feed line coming out of the cable tray removed at the first splice I verified hot to ground, hot to neutral, and neutral to ground all measured off scale high (>2200M ohms) on a Fluke 1503 with 1 kV test voltage.

Which pretty much rules out a wiring fault in the wall. This is the same test I did before commissioning the wiring and it passed at that time with the same result.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Easy enough to swap the breaker with another and see if problem follows.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Most breaker boxes you can just pop out breakers without having to kill main power. Just need to be careful, and make sure they are off. I tape barrels of screwdrivers when working with live power in case something slips.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg Yeah. Way back I used to work for an AV company, and we'd always have to tie directly in breaker boxes at venues, usually a 400 amp three phase service. Sometimes in sketchy venues there was no disconnect. You could see chunks of tools welded onto the box where others had slipped.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Random thought while assembling a PCB: Has there ever been a literal SHTF situation? As in, fecal matter impacting a rotating air circulation device?

How would such a situation arise, considering that plumbing and HVAC are (normally) kept quite separate from one another?

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg If you had pet monkeys, I could see some scenarios...

azonenberg, to random
@azonenberg@ioc.exchange avatar

Does ST (or anyone really, but ideally a STM32 variant) have any Cortex-M based MCUs with multiple IO banks and separate VCCIO for each?

I find I need e.g. 3.3V and 1.8V GPIOs in a lot of applications and I have to throw external level shifters or a CPLD or something onto the board.

Would be handy if the micro could just run a couple of IO ports at a different voltage level.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg I usually see a separate domain on GPIOG. So maybe larger packages? I have it on STM32L4S5QII and I think I've seen it on the U5 series (which also has a USB HS phy built in).

  • All
  • Subscribed
  • Moderated
  • Favorites
  • anitta
  • cubers
  • magazineikmin
  • Youngstown
  • mdbf
  • rosin
  • slotface
  • thenastyranch
  • InstantRegret
  • PowerRangers
  • kavyap
  • vwfavf
  • tsrsr
  • DreamBathrooms
  • Leos
  • everett
  • GTA5RPClips
  • khanakhh
  • tacticalgear
  • ngwrru68w68
  • Durango
  • ethstaker
  • modclub
  • tester
  • cisconetworking
  • osvaldo12
  • normalnudes
  • provamag3
  • All magazines