azonenberg,
@azonenberg@ioc.exchange avatar

Dream MCU wishlist item 732: Simple, high-speed serial protocol for fast memory mapped point-to-point IO.

Basically "PCIe lite". 8b/10b coded ~1 Gbps full duplex LVDS with packetized memory read/write requests bridged directly to AHB on the MCU side.

But no PnP enumeration, no device addressing, no request reordering, none of the other complexity of full PCIe. Something you can hang off a Cortex-M7 and use for interfacing to a lower end FPGA faster than QSPI.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg ST has a 8/16 bit PSSI that shares the DCMI interface on some MCU's. I use it to grab 8 bit data from an ice40, and I send commands over SPI. No reason you couldn't do it all on the PSSI port. Lots of traces though.

azonenberg,
@azonenberg@ioc.exchange avatar

@0h00000000 Yes that's my point. 16 bit parallel is enormous.

On the process nodes modern MCUs use (90-45nm ish) you could easily fit a ~1 Gbps LVDS SERDES without much trouble.

0h00000000,
@0h00000000@ioc.exchange avatar

@azonenberg What about MIPI? I think I read something about sending commands, and using virtual channels. NXP has a M7 with CSI, and ST has the N6 with CSI whenever its released in 100 years or whatever.

azonenberg,
@azonenberg@ioc.exchange avatar

@0h00000000 Not sure if ST has any with both CSI and DSI usable at once.

But that might work for interfacing to UltraScale parts that have native D-PHY.

It'd be annoying shoehorning arbitrary data into an interface meant for video though. For now quad SPI seems the sweet spot.

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