@azonenberg@ioc.exchange
@azonenberg@ioc.exchange avatar

azonenberg

@azonenberg@ioc.exchange

Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"

Toots searchable on tootfinder.

This profile is from a federated server and may be incomplete. Browse more on the original instance.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Soooo I think I may have finally put a bookend on my UPS saga.

Background: during the power outages a few weeks ago, I had the UPS shut down twice (once during the initial outage, second during generator fuel tank refill) when the battery gauge suggested i should have had plenty of juice left.

The first Eaton support guy I talked to said the unit was defective and I had to scrap it and shell out >$4K for a new UPS. Obviously I decided to do a bit more digging before taking that step.

Well, turns out after talking to another support rep that I've been hit by a 9PX series firmware bug he's seen once in his career. Conditions which are not fully understood (but are possibly related to swapping the network management card) result in the "low battery warning" threshold being set to 90% instead of the default 20%. This setting is apparently confusingly named and is actually the low battery shutdown threshold.

So it was draining 10% of the UPS capacity then shutting down thinking the battery was empty.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Some insights from my last poll (apparently it's not possible to make a "anyone can see, only followers can vote" poll so it's followers-only)...

Roughly 1 in 6.5 of my followers are trans (about three times the 5% rate reported in a Pew Research survey from 2022). Of the trans folks, about a third are also furries.

I figured there would be a lot of each, but the amount of overlap (especially the lack of cis furries) surprised me: if you're furry and follow me, there's a 71% chance you're trans.

Stormgren, to random
@Stormgren@obsidianmoon.com avatar

The fact that there are QSFP and OSFP pluggable EDFAs somehow feels sorta wrong. I really don't want to know how noisy those things are, and yet, I can see how useful they might be for datacenter interconnect types. I hate to lose switchports to something better handled by a 1U combiner/amplifier shelf in that application.

Though the fact that this means that the CS connector has gained traction as a result is also not making me happy, because what we needed was something even SMALLER than LC, said no one ever. Like, seriously? At least it's push-pull instead of locking tab.

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren Wait, so it ignores the host facing serdes lines and just uses it for power? Optical in, optical out, using the sfp form factor because of convenience??

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren Yeah I figured there were diagnostics on the I2C.

But as an FPGA guy who is used to scrimping and saving to put every last transceiver lane to good use, the idea of a QSFP that just ignores them rubs me the wrong way :)

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren You want something really insane / offensive, try my dream (which I never had time to implement) of shoving an ESP32 or similar into a SFP+ form factor with a single SMA connector on the front.

Slap it in a switch port and turn it into a single antenna (non MIMO) wifi AP.

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren But that was mostly a "for the lulz" concept not something I seriously planned to deploy anywhere.

My own switch designs are going to be far more sane, for LATENTRED I'm now looking at 2x SFP28 uplink + 48x 10/100/1000baseT RJ45 ports (4x VSC8512 12-port QSGMII PHY line card)

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren My azonenberg/latentpacket repo has all of the networking stuff but yeah I probably need to update the high level project docs.

The high level goal is a layer 2 (to start), possibly with some layer 3 functionality in the future, switch that's simple, no frills, and fast.

I don't need support for 30 different kinds of multicast routing and DECnet and AX.25 and IPoAC.

Just give me a basic, 1990s style fixed function CAM ASIC style, switch with as few features and as little attack surface as possible, but also modern 10/25G interface support and good power efficiency.

So the vision is a switch with a dedicated 1000baseT SSH management interface and RS232 console port connected to the management CPU, while all switch fabric ports are completely independent of management and cannot talk to the management engine (there will be no "slow path", the CPU cannot see traffic going to/from switch ports).

I don't need a lot of bells and whistles. Just port based VLANs, 802.1q, ability to force ports to specific speed and maybe duplex states, access to diagnostics like performance counters and error rates, and probably eventually some kind of port mirror/capture capability.

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren LATENTPINK was the scaled down R&D testbed (which is switching packets now including port VLANs and inbound 802.1q, but has incomplete support for outbound 802.1q tag insertion) with only 12 ports and a single SFP+ uplink.

This used a Kintex-7 FPGA (XC7K160T) but it filled up fast enough that I didn't think I would be able to fit my initial 24 port goal into the same space.

The new concept for LATENTRED scales up to an UltraScale+ FPGA and 36-48 ports (dependent on which FPGA I go with, as well as exact details of things like front panel layout).

azonenberg,
@azonenberg@ioc.exchange avatar

@Stormgren Yeah I have plans for higher end hardware with at least 100G on it, but that's going to be the successor (LATENTORANGE). Mix and speed of ports is TBD.

I plan to build two LATENTRED systems to replace my four aging Catalyst 2970G's, then at some point in the indefinite future after that, replace my Nexus 3064X with a LATENTORANGE.

gsuberland, to random
@gsuberland@chaos.social avatar

nothing says "normal sleep schedule" like watching a bps space video at 4.30am

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland Gonna go drink some carbonated milk while you watch?

azonenberg, to random
@azonenberg@ioc.exchange avatar

New toy just showed up in the mail... It's my beta ThunderScope!

Will start playing with it after work but here's some quick unboxing pics.

Black Pelican case labeled "ThunderScope" with "made in Canada" "OSHW", and "EEVengers" logos on it
Black instrument case in foam cutout with four BNCs on one side and two on the other, labeled "ThunderScope Beta 2"

azonenberg,
@azonenberg@ioc.exchange avatar

@wa7iut It's a Thunderbolt3 connected oscilloscope that should set new records in streaming data rate.

It's only a HMCAD1520 ADC (1 Gsps 8 bit or 640 Msps 12 bit, shared among 1/2/4 channels) so not super crazy on the analog side of things...

... but it's a direct PCIe-over-Thunderbolt connection that should be able to stream all of the ADC output to a PC, continuously!

azonenberg,
@azonenberg@ioc.exchange avatar

@unlambda Yep. But most excitingly, our first official instrument vendor partner adopting ngscopeclient as the user interface, rather than us building support on as an afterthought.

This is my dev scope to work out any remaining integration issues in the driver before the crowdfunding campaign goes live.

And I really want to buckle down in the next few months and get a lot of little usability issues around packaging and documentation taken care of before these things start getting in end users' hands.

azonenberg,
@azonenberg@ioc.exchange avatar

@ftg @wa7iut The antialiasing filter is in the frontend PGA and afaik can be switched off too.

So you can undersample out to something like 900 MHz frontend BW if you want to do fancy RF DDC stuff.

But for higher freq work you'd likely need an external mixer stage.

soatok, to random
@soatok@furry.engineer avatar

It’s Time for Furries to Stop Using Telegram

I have been a begrudging user of Telegram for years simply because that's what all the other furries use. When I signed up, I held my nose and expressed my discontent at Telegram by selecting a username that's a dig at MTProto's inherent insecurity against chosen ciphertext attacks: IND_CCA3_Insecure. Art: CMYKat I wrote about Furries and Telegram before, and included some basic privacy recommendations.

http://soatok.blog/2024/05/14/its-time-for-furries-to-stop-using-telegram/

azonenberg,
@azonenberg@ioc.exchange avatar

@gearlicious @soatok @GrapheneOS The last time I had to engage with a community that only existed on Telegram I ran the PC version in a virtual machine.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Optics nerds: What's the easiest, lowest cost way to build something that focuses a lot of light from a fairly wide (say 90 degree, give or take a bit) FOV into a spectrometer with a SMA 905 fiber input?

Goal is to collect UV-VIS-NIR spectra of the night sky (particularly interested in both light pollution and auroras) over as much of the 200-1200nm range as I can get with low-cost optics (i.e. I don't want to spend extra to get a bit further outside visible, but will take what I can get easily).

Since the device will be operated outside at night, it can be open frame (no need for any exterior light-shield tube, only mechanical support components).

My initial thought is some kind of 80/20 based frame holding a cheap Fresnel lens at one end, with the spectrometer mounted at the focal point (no fiber, directly bolted to a bracket at the focal point) with a cosine corrector on the input to increase the size of the entrance pupil and provide a bit of tolerance for misalignments.

azonenberg,
@azonenberg@ioc.exchange avatar

@xaseiresh That's why the plan was to put a cosine corrector on the fiber input and focus the light from the sky down onto the surface of the corrector, giving me a nice parallel input to the spectrometer.

azonenberg,
@azonenberg@ioc.exchange avatar

@xaseiresh I want the spectrum of a large area. The cosine corrector has a PTFE diffuser in it, so my thought was that if I were to focus the image of the entire night sky down onto this ~4mm disk, I'd have fairly uniform representation of the whole sky at the other end of the fiber with all spatial information discarded.

azonenberg,
@azonenberg@ioc.exchange avatar

@xaseiresh (or at least, the fraction of the night sky within the FOV of the objective lens)

gabrielesvelto, to random
@gabrielesvelto@fosstodon.org avatar

I love our users: I went over two bugs, one in Thunderbird where the user was trying to drag 5k contacts to the "To" field of a new email and the other in Firefox with the user trying to upload 100k files in one go to GDrive.

While these are extreme cases they should work. If we can handle them gracefully we can handle anything, so we should strive to make these cases work.

azonenberg,
@azonenberg@ioc.exchange avatar

@Hovedorganet With BCC, they don't see your email (so if they reply-all the other 4999 people don't get it).

ajroach42, to random
@ajroach42@retro.social avatar

I'm working on a little portfolio site to make it easier for people to know that I am accepting freelance work.

It's a work in progress right now.

https://impractical.computer/

I am accepting productive feedback, if you have any.

azonenberg,
@azonenberg@ioc.exchange avatar

@ajroach42 Just following up, did you hear anything from your candidate or are they not interested or what?

ashten, to random

new merch! cuz im getting desperate to pay the bills!

100% naturally sourced!

this is a joke, if its not obvious

azonenberg,
@azonenberg@ioc.exchange avatar

@ashten It's all your fault I went grocery shopping earlier and couldn't unsee this as I walked past the dairy shelf.

azonenberg, to random
@azonenberg@ioc.exchange avatar

New thread on my big ongoing embedded project since the other one was getting too big.

To recap, this is a pilot project for a bunch of my future open hardware T&M and networking projects, validating a common platform that a lot of the future stuff is going to run on.

The primary problem it's trying to address is that I have a lot of instrumentation with trigger in/out ports, sometimes at different voltage levels, and I don't always have the same instrument sourcing the trigger every time.

So rather than moving around cables all the time and adding splitters, attenuators, amplifiers, etc. to the trigger signals I decided to make a dedicated device using an old XC7K70T-2FBG484 I had lying around.

Of course, as with any project, there was feature creep.

I'm standardizing on +48V DC for powering all of my future projects as it's high enough to move a lot of power but low enough to be mostly safe to work around live. So I needed to design and validate an intermediate bus converter to bring the 48 down to something like 12 for the rest of the system to use.

The FPGA has four 10G transceiver pairs on it. I used one for 10GbE (not that I need the bandwidth, but I was low on RJ45 ports on this bench and had some free SFP drops) and the rest are hooked up to front panel SMA ports (awaiting cables to go from PCB to panel) to generate PRBSes for instrument deskew.

Since I'm pinning out the transceivers and am planning to build a BERT eventually, I added BERT functionality to the firmware as well (still need to finish a few things but it's mostly usable now).

And since I have transceivers and access to all of the scope triggers, it would be dumb not to build a CDR trigger mode as well. That's in progress.

azonenberg,
@azonenberg@ioc.exchange avatar

And after fixing some bugs in the QSPI-APB bridge (>2 byte burst transactions on the QSPI were not correctly incrementing the address when translating to consecutive APB transfers), I have the curve25519 accelerator accessible over APB.

There's still some refactoring needed to tidy up the code (I want to do hierarchical APB with multiple levels of decode so I don't have to pass multiple bus segments across hierarchical boundaries, and move some CDCs across module boundaries to reduce duplication in the RTL, etc).

At this point the only registers left on the legacy bus are the IRQ status register, the 10GbE link status register, the SERDES DRPs, and the Ethernet TX/RX FIFOs.

Still another couple evenings probably to finish refactoring all of this to run over APB, then I can start testing direct memory mapping of the registers rather than the indirect access I'm using now.

azonenberg,
@azonenberg@ioc.exchange avatar

So far all of my code has ignored PSTRB (full width 16 bit writes only).

But Ethernet frames can be an odd number of bytes in length, so I need to handle the case of CS# rising midway through a word and sending this as a partial width (byte masked) APB transfer.

azonenberg,
@azonenberg@ioc.exchange avatar

That actually wasn't that hard to implement.

It's now working successfully, at least in the TX direction (RX is still using the legacy bus).

So now I have what is probably the world's first and only (because why would anyone else ever attempt it?) 10GbE MAC which allows you to transmit frames over APB. Not AXI, not AHB. Just plain old APB.

Obviously it can't get close to saturating the link, but the other end of the APB bus is a 50 MHz quad SPI link anyway. The intent here is that you can have 99% of the packets coming to/from the MAC terminate on the FPGA in full-speed accelerator blocks with only management traffic going to the MCU.

I just don't have any of that fast path implemented in my current FPGA design (yet).

azonenberg,
@azonenberg@ioc.exchange avatar

Almost done with the APB refactoring despite lots of other things going on keeping me from spending a lot of time on it.

Now at 40% LUT load so plenty of room to expand for new features (in particular, CDR triggering) in the future.

Purple on south edge = Curve25519 accelerator

Pink at north area: debug ILA, currently looking at CDR trigger signals in anticipation of me actually implementing CDR trigger functionality at some point

Dark blue mostly in northeast: BERT / CDR trigger subsystem

Light blue: Ethernet MAC/PCS logic

Green: actual trigger crossbar muxing (tiny portion of overall logic, lol)

Red = management logic (QSPI bridge, legacy bus logic, FIFOs for MCU Ethernet TX/RX)

Brown = low speed APB peripherals (tachometers for fans, front panel SPI bus interface, etc)

Still some additional refactoring and code cleanup pending, plus converting the 1000baseT TX FIFO, the shared Ethernet RX FIFO, and the interrupt status register to APB. Hoping to get that done in the next couple days.

  • All
  • Subscribed
  • Moderated
  • Favorites
  • •
  • anitta
  • InstantRegret
  • magazineikmin
  • Youngstown
  • everett
  • thenastyranch
  • slotface
  • vwfavf
  • mdbf
  • rosin
  • kavyap
  • khanakhh
  • cubers
  • PowerRangers
  • provamag3
  • DreamBathrooms
  • tacticalgear
  • Durango
  • ethstaker
  • osvaldo12
  • ngwrru68w68
  • cisconetworking
  • tester
  • GTA5RPClips
  • normalnudes
  • modclub
  • Leos
  • megavids
  • All magazines
    •