@azonenberg@ioc.exchange
@azonenberg@ioc.exchange avatar

azonenberg

@azonenberg@ioc.exchange

Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"

Toots searchable on tootfinder.

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johncarlosbaez, (edited ) to random
@johncarlosbaez@mathstodon.xyz avatar

About half the periodic tables you see are wrong. The only question is: which half?

Check out this one from Encyclopædia Britannica. See the row of elements in yellow-green near the bottom? They start with element 58, cerium and end with element 71, lutetium. There are 14 of them. They're called 'lanthanoids'.

Okay. But note that lanthanum itself, element 57, is up somewhere else. It's also called a lanthanoid, and it's under two other elements in yellow-green called 'rare earths'.

Next compare the periodic table on Wikipedia.

(1/4)

azonenberg,
@azonenberg@ioc.exchange avatar

@dearlove @johncarlosbaez That's the format I prefer.

azonenberg, to random
@azonenberg@ioc.exchange avatar

New thread on my big ongoing embedded project since the other one was getting too big.

To recap, this is a pilot project for a bunch of my future open hardware T&M and networking projects, validating a common platform that a lot of the future stuff is going to run on.

The primary problem it's trying to address is that I have a lot of instrumentation with trigger in/out ports, sometimes at different voltage levels, and I don't always have the same instrument sourcing the trigger every time.

So rather than moving around cables all the time and adding splitters, attenuators, amplifiers, etc. to the trigger signals I decided to make a dedicated device using an old XC7K70T-2FBG484 I had lying around.

Of course, as with any project, there was feature creep.

I'm standardizing on +48V DC for powering all of my future projects as it's high enough to move a lot of power but low enough to be mostly safe to work around live. So I needed to design and validate an intermediate bus converter to bring the 48 down to something like 12 for the rest of the system to use.

The FPGA has four 10G transceiver pairs on it. I used one for 10GbE (not that I need the bandwidth, but I was low on RJ45 ports on this bench and had some free SFP drops) and the rest are hooked up to front panel SMA ports (awaiting cables to go from PCB to panel) to generate PRBSes for instrument deskew.

Since I'm pinning out the transceivers and am planning to build a BERT eventually, I added BERT functionality to the firmware as well (still need to finish a few things but it's mostly usable now).

And since I have transceivers and access to all of the scope triggers, it would be dumb not to build a CDR trigger mode as well. That's in progress.

azonenberg,
@azonenberg@ioc.exchange avatar

Next step is to be able to DFU the FPGA.

Coming along nicely, but not done yet. I'm parsing the entire .bit structure on the fly in order to enable editing some config settings for multi-boot, although for now the data is being passed through to the write buffer unchanged (then discarded since I've implemented flash erasing but not writes).

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