I don't see many KiCad projects with detailed notes in the board files or schematic, which is kinda sad because it's a great way to keep notes for reference and important design descriptions.
My KiCad schematics and board files are absolutely littered with notes, with things from calculations for things to why things are done they way they are.
I wish more people would do it, makes things easier on everyone.
@gregdavill Yeah, I find a lot of people really don't use the hierarchical sheets to their full potential, if they even use them at all, they just bump the page size.
I also wish people would stop just smearing global labels over everything,.
I've been thinking about dedicating the root sheet to a block diagram and stuff like that, but I tend to to just interleave that stuff within the schematic pages. but having a dedicated overview page is not a bad idea.
Has anyone used OpenEMS to calculate trace impedance profiles from a PCB stackup before?
I'm looking around for decent and fast 2d field solvers for that kinda thing but outside of like 4 HUGE and expensive software suites there really isn't anything for the at home catgirl
Something that probably only I would find useful, but would be nice in KiCad is the ability to assign a nested sheet a schematic symbol, and have the pins match up to the sheet pins.
What do you think about someone out there making a "synthesising simulator" where one codes in a custom HDL and compiles it… — That sounds like an interesting project!
Personally I wouldn't bother with a custom HDL, but that's just me.
If I was workin… https://retrospring.net/@lethalbit/a/112432223700575992
And then I have one i'm working on but rather than 7400-series logic i'm doing discrete FET logic (but it still needs a lot of work but i've been busy) https://github.com/lethalbit/discretize
No PnR tho, but I was working on KiCad eeschema netlist export, and re-usable macroblocks for pcbnew.
I fixed my cohost bot, logicbot to allow for more than one output and also fixed the bug that was causing the netlists to be reduced to pure AOI netlists, so now we have things like muxes, and XOR gates and all that good stuff,
The general gist of how it works is that it randomly picks a number of expressions to generate (1 to 4) then for each expression it randomly picks how many terms it will have.
Once that's done, it generates a LUT with that many columns and fills it out randomly.
The LUT is then converted into Algebraic Normal Form and then either expressly simplified or not.
Once that's done it generates Verilog which is cammed into Yosys with some processing, then the netlist SVG is generated from that.
You'd then jump to the stub which would replace the old kernel, and then poke the new kernel to deserialize the kernel structures then resume into userspace.
I wouldn't want to actually use that, but I think it would be a funny, and very high effort shitpost.
@azonenberg I have something like that in the pipeline! It'll even build the cross-compilers for you if it knows how! (that's the plan anyway :v, too many projects in the works)