I fixed my cohost bot, logicbot to allow for more than one output and also fixed the bug that was causing the netlists to be reduced to pure AOI netlists, so now we have things like muxes, and XOR gates and all that good stuff,
The general gist of how it works is that it randomly picks a number of expressions to generate (1 to 4) then for each expression it randomly picks how many terms it will have.
Once that's done, it generates a LUT with that many columns and fills it out randomly.
The LUT is then converted into Algebraic Normal Form and then either expressly simplified or not.
Once that's done it generates Verilog which is cammed into Yosys with some processing, then the netlist SVG is generated from that.
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