shachaf,
@shachaf@y.la avatar

Is there a way to convince clang/LLVM to do 16-byte atomic loads with SSE instead of lock cmpxchg16b?

pervognsen,
@pervognsen@mastodon.social avatar

@shachaf I think a guarantee (AVX CPUID flag must be set, natural alignment is a requirement, etc) was only very recently (I found an SO answer that says 2021) added to Intel's instruction manual so compilers are probably lagging. In the mean time you can implement it yourself using intrinsics.

pkhuong,

@pervognsen @shachaf Wait, when did we get that guarantee? Intel only, I guess?

rygorous,
@rygorous@mastodon.gamedev.place avatar

@pkhuong @pervognsen @shachaf I don't thing it's even in the manuals, it was a gentleman's agreement on LKML or something along those lines.

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