Enhancing the Simulation Testbench for VHDL-based FPGA DesignsPart 3: Advanced Testbench for a Complex DUT

In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the high risk this represents – not to mention all the late fixes required or, even worse, the escape of bugs into the customers’ products.

The two prior versions of this seminar are also available on Aldec's site. It's a generally good overview of verification methodologies and specifically using UVVM (Bitvis' Universal VHDL Verification Methodology, a VHDL specific verification framework and toolset).

US and EU times available, though I think the link points primarily to the EU timezone.