VHDL

Enhancing the Simulation Testbench for VHDL-based FPGA DesignsPart 3: Advanced Testbench for a Complex DUT (www.aldec.com)

In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the...

Blending GNU Radio and Aldec Riviera-PRO for verification of Software Defined Radio

This whitepaper https://www.aldec.com/en/company/blog/190--development-of-real-time-sdr-systems-with-aldec-hes describes a method by which the designer can leverage the rapid signal prototyping capability in GNU Radio and use it in co-simulation with Aldec Riviera-PRO....

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