> The problem is that Verilog was originally designed as a language to describe simulations
this is a common misconception! it's excusable, given that I work on FPGA (incl. Verilog) toolchains for a living and thought so for the longest time
there is a HOPL IV paper on Verilog and the people who designed it say they designed it for synthesis from the beginning, with a fairly detailed description of how they prepared it for that.
#lisp#CommonLisp#gopher#vhdl
I talk about the trivial basis for this month on a microcode implementation for @amszmidt 's #CADR4 lisp machine in vhdl using a mixture of lisp and Reichenbacher. links v
Time for my #introduction to the Fediverse! :masto_love:
Clash is an open source functional hardware description language built on #Haskell.
The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your #FPGA and #ASIC designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output #VHDL / #Verilog / #SystemVerilog code for synthesis.
I don't know who all uses Emacs for VHDL but the vhdl-mode major mode is pretty great for the language. Of course, use whatever makes you the most productive. The following is from the vhdl-mode maintainer, Reto Zimmerman....
This whitepaper https://www.aldec.com/en/company/blog/190--development-of-real-time-sdr-systems-with-aldec-hes describes a method by which the designer can leverage the rapid signal prototyping capability in GNU Radio and use it in co-simulation with Aldec Riviera-PRO....
Have you fine Mastodon folks seen this awesome work?
First ever raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA! @suarezvictor's fantastic work w/ CflexHDL + PipelineC! #raytracing#graphics#hardware#gamedev#hdl#verilog#vhdl#eda
OC Latest vhdl-mode package for Emacs
I don't know who all uses Emacs for VHDL but the vhdl-mode major mode is pretty great for the language. Of course, use whatever makes you the most productive. The following is from the vhdl-mode maintainer, Reto Zimmerman....
Blending GNU Radio and Aldec Riviera-PRO for verification of Software Defined Radio
This whitepaper https://www.aldec.com/en/company/blog/190--development-of-real-time-sdr-systems-with-aldec-hes describes a method by which the designer can leverage the rapid signal prototyping capability in GNU Radio and use it in co-simulation with Aldec Riviera-PRO....