alcinnz,
@alcinnz@floss.social avatar

Now I'm going though my previous writing on my hypothetical internet-communicator & adjusting it to pretend like I had the "FPMA" coprocessor in there from the beginning...

Also for the sake of consistency I wrote that the Input Preprocessor and include a CRC circuit to be used by parsers for common fileformats & wire protocols.

And I've refined my description of the "Arithmetic Core" to better suit the programs I'd run in it.

1/2

alcinnz,
@alcinnz@floss.social avatar

Primarily I extended my description of FLAGS register in this hypothetical rudimentary 16bit RISC machine, adding bits for:

  • Indicating when the processed datastream is ending.
  • Enable a different memory architecture I described elsewhere for LZ compression
  • Enable autoincrementing ADDR register to simplify code processing data in RAM.

Also I refined my description of pausing programs, running trivial tasks, & operating the "privileged mode" to access entropy, clock, etc.

2/2Fin!

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