jos1264, Manta: An Open On-FPGA Debug Interface https://hackaday.com/2024/05/01/manta-an-open-on-fpga-debug-interface/ #debuginterface #logicanalyser #logicanalyzer #ToolHacks #amaranth #ethernet #verilog #FPGA #fpga #uart
didier, Anyone interested in checking out some Analogue Pocket development, come by the newcomer zone and say hi!
tommythorn, Ok, Google couldn't help, so suggestions solicitated!
I use both Icarus Verilog and Verilator for simulation and initialize my rams with
$readmemh(`INIT_MEM, code);
The drawback of this is that the produced simulation binary is tied to the
-DINIT_MEM=prog.hex
value used at compilation time. I would like to reuse the simulation binary on multiple workloads. Is there a way that works for both Icarus and Verilator?
didier, Looking to get started with #AnaloguePocket development or just curious on how it's done? I got ya...
Just merged my tutorial site with the repo hosting all the sample code.
glairedaggers, today's lunch break fix: HELL YEA WE ARE COOKIN WITH GAS NOW BAYBEEE
itnewsbot, QSPICE Picks Up Where LTSpice Left Us - [Mike Engelhardt] is a name that should be very familiar to the hardcore electroni... - https://hackaday.com/2023/08/25/qspice-picks-up-where-ltspice-left-us/ #mikeengelhardt #softwarehacks #mixed-mode #simulation #toolhacks #ltspice #verilog #analog #power #qorvo #spice #c