> The problem is that Verilog was originally designed as a language to describe simulations
this is a common misconception! it's excusable, given that I work on FPGA (incl. Verilog) toolchains for a living and thought so for the longest time
there is a HOPL IV paper on Verilog and the people who designed it say they designed it for synthesis from the beginning, with a fairly detailed description of how they prepared it for that.
Ok, Google couldn't help, so suggestions solicitated!
I use both Icarus Verilog and Verilator for simulation and initialize my rams with
$readmemh(`INIT_MEM, code);
The drawback of this is that the produced simulation binary is tied to the
-DINIT_MEM=prog.hex
value used at compilation time. I would like to reuse the simulation binary on multiple workloads. Is there a way that works for both Icarus and Verilator?
The NYD 24 Global Stream Parade officially kicks off in les than an hour at 0100 UTC.
This will be our thread for announcing upcoming stops on the parade route which can be seen at: https://radiofreefedi.net/nyd24
We and the broadcasters will use #NYD24Parade if you want to keep an eye out, or mute for the day. Boost the participants and let's celebrate discovering some of your fedi streaming friends.
Time for my #introduction to the Fediverse! :masto_love:
Clash is an open source functional hardware description language built on #Haskell.
The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your #FPGA and #ASIC designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output #VHDL / #Verilog / #SystemVerilog code for synthesis.
This morning I’ve been working on eForth for the #Transputer emulator, changing its example UART I/O code to use IServer protocol requests, and changing its use of macros for defining Transputer op codes with DB directives to use actual instructions that my assembler understands. There’s probably still lots to work on, but going to try a first boot later :)
Have you fine Mastodon folks seen this awesome work?
First ever raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA! @suarezvictor's fantastic work w/ CflexHDL + PipelineC! #raytracing#graphics#hardware#gamedev#hdl#verilog#vhdl#eda