If any STMicro engineers follow me, I have a challenge for you.
Release a new STM32, any size, in which at least one IO bank is contiguous on die (i.e. Px0 - Px15 are on adjacent bond pads with no other pins in between them aside from Vdd/Vss) and, on packaged chips, is placed in at least roughly the same corner of the package.
@azonenberg Hell some QFN or 1mm or .8mm BGA with <200 pins (full breakout on 2 routing layers with 6/6 or larger) and more than one IO voltage bank would be the dream. And I'll take any MCU with good SVD and GCC/LLVM support, doesn't need to be ST.
@attilakinali For small volume protos I'm seriously looking into doing that myself.
As in, buying a bunch of STM32s in WLCSP and making a fanout substrate that breaks out the solder-bumped die to a sane pitch BGA with a few substrate bypass capacitors. Maybe even slap some tiny level shifters on there too so I can have one "bank" of IOs running at say 1.8V.
But i don't understand why they can't put that in the silicon, and offer a package somewhere between 144-TQFP and 0.5mm BGA. There's clearly (I assume) demand.
@azonenberg I think most EEs who don't do tiny stuff are afraid of BGA because it requires special tooling and inspection. So they rather go for a QFP than for BGA.
Yes, I know that 1mm/0.8mm pitch BGA are easier to solder and have a higher yield than than DFN and QFN which all EEs I know will happily use, but that's the sentiment I've seen.
@attilakinali Yeah my pref is large BGA > DFN/QFN > fine pitch BGA. With QFP as a last resort because of awful yield and enormous and poor SI and generally a pain in the neck to work with. Especially the 144TQFP monster.
@azonenberg Poor SI? My experience is that QFP is pretty easy to inspect visually. Yes, it uses an awful amount of space, but otherwise it's a pretty tame packaging.
@attilakinali I'm talking about the incredibly long leadframe and bondwires adding tons of ESR/ESL to every pin, and probably not being super well impedance matched either in most cases.
And yes QFP is easy to inspect but I've also had poor assembly yield (they bridge way more easily than QFN/DFN packages).
Add comment