Returning to the #Datapoint simulator to try and fix a thorny issue that's been eluding me for a while.
The four chips at the bottom are '193 counters which normally house the program counter. Above are a row of '153 4-to-1 multiplexers. These can load an address from the stack, the H, L registers or the temp address register (for inline jump, call addresses).
Executing the LAM instruction (equivalent to LD A,(HL) in Z80) involves storing PC on the stack, asserting /ADDR_SEL.HL to set the multiplexers and /ADDR.LOAD to latch the data in the counters. Data latched whenever the signal is low.
But the simulator loads all 1 bits - the 'off' value for the multiplexers.
/ADDR_SEL.HL and /ADDR.LOAD are driven by the same circuit, timing separated by gate delays. Presumably this works in the original machine but my simulator is experiencing some kind of race condition which keeps.
I've tweaked the simulated gate delays for the multiplexers and the timing logs show they're changing /after/ LOAD is cancelled. Next stage is to add some detailed logging to the chips to see what's happening.
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