Anybody familiar with the #SystemVerilog LRM who can tell me if it's legal to use an integer or logic (vs a genvar) as an index into an array of interfaces?
where upstream and downstream are both interface objects.
Vivado complains when I do this. I can achieve the same result in two steps by creating a wire[DATA_WIDTH-1:0][NUM_PORTS-1:0] prdata, then assigning it to the interface value with a generate loop, then doing a normal behavioral mux on this vector, so it's not the end of the world, but it does make the code uglier.
Time for my #introduction to the Fediverse! :masto_love:
Clash is an open source functional hardware description language built on #Haskell.
The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your #FPGA and #ASIC designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output #VHDL / #Verilog / #SystemVerilog code for synthesis.