Enhancing the Simulation Testbench for VHDL-based FPGA DesignsPart 3: Advanced Testbench for a Complex DUT (www.aldec.com)
In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the...