Welcome to /m/VHDL

Welcome to a VHDL based magazine on kbin. I have left Reddit and will not be voluntarily returning and I wanted a spot where conversations and news might crop up about VHDL.

I'm a near 30 year veteran EE with the last 20 being nearly entirely dedicated to #FPGA design, primarily using #VHDL as a design language. (I'm also facile with #Verilog, but I don't care for the design patterns and the language all that much.) I try to stay up to date with what's going on in the realm of design and verification.

I put some basic guidelines on the sidebar. I figure we're all professionals (or professional adjacent) and can behave as adults. I'll moderate as best I can, hopefully it'll be a pleasant experience.

I don't know that kbin has code formatting just yet, so it's greatly appreciated if one uses pastebin or similar snippet repositories until the forum software develops.

Good luck with your designs. I hope to see folks using the magazine!