azonenberg,
@azonenberg@ioc.exchange avatar

All of the open ECP5 tooling work is cool and all, but a little on the small/slow side for my taste.

Is anyone working on open tools for Lattice Avant-X yet?

GyrosGeier,
@GyrosGeier@hachyderm.io avatar

@azonenberg the number of people who can verify that a SERDES is behaving correctly is not that large.

azonenberg,
@azonenberg@ioc.exchange avatar

@GyrosGeier I'll gladly help support the effort with PHY validation testing if someone gets to that point.

cr1901,
@cr1901@mastodon.social avatar

@azonenberg
> small/slow
> 85000 LUTs

While I agree that's a medium-small to medium (at best) FPGA in the grand scheme of things, I still wince a bit :P.

azonenberg,
@azonenberg@ioc.exchange avatar

@cr1901 I mostly mean "slow" as in "no 10/25G SERDES". Although I'm sure the fabric isn't as fast as e.g. Kintex-7 or UltraScale+.

But that's the class of FPGA most of my current and future projects are targeting.

whitequark,
@whitequark@mastodon.social avatar

@azonenberg @cr1901 CrossLink-NX still too slow?

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark @cr1901 No 10/25G NRZ SERDES, so yes.

All of my major upcoming projects will need 10/25/40/100GbE and/or 10 Gsps JESD204.

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