whitequark, 21 days ago Q: how do you tell an FPGA was going to be marketed for video applications? A: Ctrl+F 7
Q: how do you tell an FPGA was going to be marketed for video applications? A: Ctrl+F 7
thejpster, 21 days ago @whitequark wut? Oh! https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesigns01/71LVDSVideoInterface
@whitequark wut? Oh!
https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesigns01/71LVDSVideoInterface
thejpster, 21 days ago @whitequark I get 24 bits for RGB, and two for H and V sync. But what are the other two for?
@whitequark I get 24 bits for RGB, and two for H and V sync. But what are the other two for?
whitequark, 21 days ago @thejpster one is DE (data enable)
@thejpster one is DE (data enable)
thejpster, 21 days ago @whitequark > TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control lines- FPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC, Data Enable) Ah yes, those four control lines. https://media.digikey.com/pdf/Data%20Sheets/ST%20Microelectronics%20PDFS/STLVDS385.pdf
@whitequark
> TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control lines- FPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC, Data Enable)
Ah yes, those four control lines.
https://media.digikey.com/pdf/Data%20Sheets/ST%20Microelectronics%20PDFS/STLVDS385.pdf
whitequark, 21 days ago @thejpster iirc the last bit is just zero
@thejpster iirc the last bit is just zero
thejpster, 21 days ago @whitequark hmm. you could do a lot with a ~75 Mbit/sec uni-directional side-channel.
@whitequark hmm. you could do a lot with a ~75 Mbit/sec uni-directional side-channel.
whitequark, 21 days ago @thejpster yeah, some vendors probably put audio into it or something
@thejpster yeah, some vendors probably put audio into it or something
whitequark, 21 days ago iCE40 for example:
iCE40 for example:
whitequark, 21 days ago ECP5 for example:
ECP5 for example:
whitequark, 21 days ago MachXO3 for example:
MachXO3 for example:
gsuberland, 21 days ago @whitequark for a moment I thought this was talking about interfacing LVDS directly to GDDRx (e.g. GDDR5) and I was mightily confused.
@whitequark for a moment I thought this was talking about interfacing LVDS directly to GDDRx (e.g. GDDR5) and I was mightily confused.
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