I’m moving to Denon HEOS. I’m hoping that something from an established audio company with a long history - rather than a tech industry start up - will mean a slower path to enshittification.
@RetroFunPL New ‘improved’ app, rewritten from the ground up.
The UX is horrible. The key pain point for me is that there doesn’t seem to be any way to connect to the NAS. Although it did work for the first five minutes, but the artists list had no A-Z quick links and I was having to scroll down through several hundred entries.
@saustrup Just something I read on the Enterprise Forever forum. The issue 4 had the Flan name on the board. Those were the boards used in the Enterprise 64s. I don’t know anything beyond that. I got the impression that was the first production run. Presumably the earlier issues were prototypes.
60 years ago today this happened. Up until then we only had 2 (TWO) channels. You nippers don’t know how good you’ve got it with your on-demand streaming services. 😎
I/O on the #Datapoint 2200 (as I'm understanding it) :
The instructions are similar to the i8008. Bits 4 to 1 of the bytecode code the I/O port. 32 addresses, but the first 8 are inputs, mapped to instructions IN 0..7. The remaining 24 are outputs mapped to instructions OUT 0..23.
The Datapoint uses the instruction EX for outputs (short for external IIRC)). Rather than port numbers it uses names. The first 8 are generic:
EX ADR
EX STATUS
EX DATA
EX WRITE
EX COM1 though EX COM4
🧵
To poll a device for input data:
Set A to device address
EX ADR ;Device selected
EX STATUS ;Prepare to read status byte
INPUT ;Read status byte
Check value. If data available:
EX DATA ;Prepare to read data
INPUT ;Read data
Data is now in A register.
However, the output port is decoded on the decoder board using bits 4..1 of the instruction register. They're exposed on pins on the processor boards edge connector.
The instruction decoding for the INPUT command looks to be partial enough that it is issued irrespective of the port address. If so another board could be decoding I4..I1 to give an input port address.
(But the pinouts for every board are unique to that board. It's possible no other board has access to them).
BTW the 'Clocks' readout on the simulator counts half cycles. The simulation takes just over 700k half cycles to run. That translated to about 35ms at the 9.84MHz crystal frequency.
@richardloxley Considering you can still get NOS for chips discontinued decades I don’t think it’s worth panicking. But a little stash never hurt anybody 🙂
I have come to the conclusion that compiler writing is in my future. I have repeatedly told myself it's a terrible idea. I have even publicly said I'm not going to do it unless someone pays me a lot of money.
But the money won't happen. I know I'm going to do it anyway.
It's a next year problem. I have other projects to complete first, plus It'll take me at least that long to gain a fraction of the knowledge I need to start.
CTRAN was the start, and it gave me a tiny taste. I even liked it.
Returning to the #Datapoint simulator to try and fix a thorny issue that's been eluding me for a while.
The four chips at the bottom are '193 counters which normally house the program counter. Above are a row of '153 4-to-1 multiplexers. These can load an address from the stack, the H, L registers or the temp address register (for inline jump, call addresses).
/ADDR_SEL.HL and /ADDR.LOAD are driven by the same circuit, timing separated by gate delays. Presumably this works in the original machine but my simulator is experiencing some kind of race condition which keeps.
I've tweaked the simulated gate delays for the multiplexers and the timing logs show they're changing /after/ LOAD is cancelled. Next stage is to add some detailed logging to the chips to see what's happening.