@azonenberg@ioc.exchange
@azonenberg@ioc.exchange avatar

azonenberg

@azonenberg@ioc.exchange

Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"

Toots searchable on tootfinder.

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azonenberg, to random
@azonenberg@ioc.exchange avatar

When a modern (LTE/5G) cellular radio is placed in airplane mode, what actually happens?

Does the entire RF chain power down? Does it just disable the transmitter? Is it still passively listening for towers so when you turn airplane mode off it knows what frequency, time slots, etc to start transmitting in? How much does this vary from radio to radio?

azonenberg,
@azonenberg@ioc.exchange avatar

@taral Yep that was part of the question, is airplane mode almost as good as a full powerdown of the radio for saving juice if you know you're out of service for a prolonged time? And how close is it to a full baseband reset?

azonenberg,
@azonenberg@ioc.exchange avatar

@taral That kinda jives with what I've seen on this phone where sometimes it shows no service in areas that I know there's a signal (probably due to the baseband getting in a bad state) and entering and leaving airplane mode usually clears it up.

gsuberland, to random
@gsuberland@chaos.social avatar

I know embedded passives are a thing, but has anyone done vertical embedded passives yet? essentially a via with a passive integrated into it.

would be kinda cool to combine it with via-in-pad so you could shove an 01005 MLCC directly under power pads for ridiculously low inductance decoupling.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland At that point you are really much better off putting the capacitor directly on the substrate / leadframe and wirebonding or soldering it, bypassing PCB inductance entirely.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Continuing LATENTPINK layout. Close to 1/3 of the way done by number of nets, although a lot of that is just adding power vias under the VSC8512 so it doesn't feel like I've done that much yet.

Also, holy capacitors Batman - this is going to be fun to hand populate! So many 0402s under the PHY. (I couldn't find any decoupling guidelines for the PHY so I may have gone slightly overkill... this isn't all of them either!)

jerry, to random

Starting a fundraiser to start up the .js and .php TLDs. I think it’s around $300k. We can DO this

azonenberg,
@azonenberg@ioc.exchange avatar

@dearchitectura @jerry .swf doesn't exist yet, right? :P

azonenberg, to random
@azonenberg@ioc.exchange avatar

Starting layout on LATENTPINK finally! Working my way out from the bottom right corner. Here's the first four baseT interfaces routed from magjacks through ESD diodes to the PHY.

The dual row magjacks get a little tight with the center-tap termination capacitors so I did the last hop from ESD diodes to the magjack on an inner layer. I needed 6-8 layers anyway to fan out the FPGA and route the QDR so why not take full advantage of it?

The VSC8512, despite being a 676 ball package, is very routing friendly. I could have escaped the baseT entirely on one layer if it wasn't for the magjack having slightly different pair ordering on the upper vs lower side (because one is tab up and one is tab down).

KiCAD overview screenshot of the entire switch board including a massive cloud of unplaced components hanging off the left of the board

azonenberg,
@azonenberg@ioc.exchange avatar

Tentative overall strategy is to route all of the baseT fabric ports along the right side and the management PHY in the top left (including local decoupling/termination passives but not the bus to the FPGA), then see how much space I have left to squeeze in power supply stuff.

Once I have the whole perimeter of the board laid out I'll then work out from the middle laying out the high speed SERDES lines, the QDR, and the [R|S]GMII to the north side PHYs.

Then management MCU, temp sensors, GPIO LEDs, and other low priority stuff can get shoehorned wherever it fits.

azonenberg,
@azonenberg@ioc.exchange avatar

@claudius I wish I only had a dozen power domains. If you count the filtered analog rails it's north of 20.

niconiconi, to random

The fact that top-of-the-line Intel and AMD desktop CPUs only requires a 4-layer PCB to work is truly mind-blowing. Power and signal integrity are obvious problems, but on a 4-layer PCB, even fanout is a problem. Who knows how many engineering hours were spent just on the pinout of the CPU sockets to make routing possible...

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @niconiconi @projectgus This is why we see all of the insanity like the little teeth on DDR routing to act as a distributed element filter to null out crosstalk because they were too cheap to jump up to 8-10L and space things out more reasonably...

azonenberg,
@azonenberg@ioc.exchange avatar

@niconiconi @gsuberland @projectgus Are PC motherboards actually made on cheap FR-4? I assumed it was at least something a little bit lower loss like FR408HR or TU-872 or similar.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland @niconiconi @projectgus 0.035 Df? Even Isola 370HR is better than that.

No wonder they have such crazy equalizers in PCIe etc.

gsuberland, to random
@gsuberland@chaos.social avatar

looking through the board file of a (confidential, leaked) Intel Cannonlake chipset platform validation motherboard and discovered it has the fancy swappable chipset mount as seen in a few recent public factory tours of Intel's labs.

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark @gsuberland For I bring you good tidings of cursed tech, which shall be to all people.

azonenberg,
@azonenberg@ioc.exchange avatar

@gsuberland i think it's more likely that it was originally 12L and you only have 10 of those, i.e. the spicy layers are missing in this dump.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Good thing I have a bunch of these in inventory now, I can't afford to wait until I retire to get some MCUs...

azonenberg,
@azonenberg@ioc.exchange avatar

@mupuf I mean that's not too horrible considering the specs (and that it's qty 1 distributor markup pricing).

550 MHz M7, SMPS+LDO, 1 MB flash, 564 kB SRAM, 201 ball BGA package, hardware crypto. I quite like them.

Trying to get hold of some of the 68-QFN version of the same die but have to date been unsuccessful without insane lead times. Digikey wants me to buy a whole case of like 1500, Mouser will sell me one-offs but they won't ship until next year. Might do that.

chjara, to random

favorite PCB solder mask color

azonenberg,
@azonenberg@ioc.exchange avatar

@chjara Blue!

azonenberg, to random
@azonenberg@ioc.exchange avatar

These new fad dog breeds are getting seriously ridiculous. A poodle and a Snickers bar, really?

(I can't be the only one who thinks that a "snickerdoodle" sounds like a close relative of a goldendoodle)

azonenberg, to random
@azonenberg@ioc.exchange avatar

Is anyone aware of a way to use a mini-split, or something in that size range, to do waste heat recovery?

Scenario:
Building contains two regions A and B, which are required by both building code and operational constraints to not have any direct air exchange (i.e. ducts from one to the other).

Region A is about 1600 ft^2 and has a conventional heat pump forced air HVAC system. Typical residential / light office class thermal loading

Region B is about 400 square feet and currently has a Mitsubishi mini split. It contains equipment running 24/7 which collectively produces >3 kW of waste heat, which the mini-split dumps outside (running in cool mode year round).

I'd like to improve the energy efficiency here if possible. The most obvious problem is that I'm burning power to dump heat from B outside to cool it in the winter, then yet more power to pump heat from outside to A. Is there any way to multiplex so I can heat A directly with waste heat from B?

azonenberg,
@azonenberg@ioc.exchange avatar

The challenge is handling mismatches: if A is still too cold I need additional heat pumped from outside, and if A is too warm I need to dump the extra heat outside

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark me neither. This is something I've been thinking of for years now due to my >$400/mo power bills (and the environmental impact of the energy usage, although they're not too bad given that the majority of our local power grid is hydroelectric).

To date I've come up empty handed.

azonenberg,
@azonenberg@ioc.exchange avatar

@uint8_t @whitequark How do those handle one room needing heating and another needing cooling simultaneously, though? And can they move heat from one indoor unit to another?

azonenberg,
@azonenberg@ioc.exchange avatar

@dascandy42 Yeah exactly. Ultimately what I want is some kind of 3-port heat exchanger with valves that lets me dump heat outside or inside depending on relative heat differences. And I don't think that exists.

azonenberg,
@azonenberg@ioc.exchange avatar

@AMS @uint8_t @whitequark Yeah some quick googling indicates I'm looking for a VRF heat pump ti do this right.

azonenberg,
@azonenberg@ioc.exchange avatar

@PaulM Interesting idea but likely not too useful. From some very rough googling a residential water heater averages under 500W average power consumption and I'm looking to get rid of 6x that. Probably not worth the effort for the minimal savings.

OTOH if I could heat most of the house for free in the winter with waste heat? That's worth it.

azonenberg, to random
@azonenberg@ioc.exchange avatar

What's the current thoughts / recommendations on ESD protection for Ethernet data lines?

I'm using three different PHY chipsets here; one is rated for 8 kV HBM while the other is only 1.75 and the third doesn't seem to have a specification.

The 8 kV one I feel OK not adding any extra protection on, but the other two I think could probably benefit from some diodes.

azonenberg,
@azonenberg@ioc.exchange avatar

@AMS I'm using UTP cabling so the shield should rarely if ever see an ESD event compared to the data pins.

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