@dlharmon You've done bare metal Zynq-7 stuff right?
Do you have any kind of blog or resources to talk about how to set up an extreme minimalist no-OS bare metal Zynq firmware?
Ideally I'd like just a single source file (not generated by vivado, something I can actually write from scratch) that I can just build with arm-none-eabi-g++, put on a SD card (zynq doesn't allow you to jtag binaries to the PS right?), and then boot up and give me some sign of life by poking a GPIO SFR or something.
Ultimately my goal is to experiment with some truly cursed things that are likely incompatible with all of the generated wrappers, petalinux, etc.
Things like having PL be a CoreSight APB bus master that can poke debug registers on the A9s.
If you want IO muxes, memory controller, etc set up, you will need to at least build and link with the ps7_init.{c,h} generated by Vivado. If you don't want that, single file should be doable. Bootgen will take an ELF.
It's possible to directly instantiate the PS7 block in RTL but probably makes more sense to make a simple block design (and script that) as detailed in the post.
@azonenberg I should also add XC7Z is much simpler than XCZU in that post but most applies. No CSU and PMU on XC7, bootrom runs on the A9 cores unlike XCZU where the first instruction run on the ARM cores is user code.
For the initial PoC goal is to keep things as minimal as possible with bitstream loaded over JTAG and the only output from the PS7 being an EMIO GPIO or something.
@azonenberg@dlharmon I briefly attempted to look into this type of thing, but instead swore off zynq as too antagonistic to this approach. The mindset of the tool writers is so mismatched that it seemed a hopeless, endless, uphill battle just to get to zero and start from scratch. If you do it you are a foolhardy hero. :-)
But unless you know of any other way that I can get a hard ARM CPU with its debug bus bridged to something I can write via FPGA (in a more performant manner than a SoC that a separate FPGA connects via a JTAG-DP), it seems the least bad of the available bad options.
@poleguy@dlharmon The use case is to explore something I back-burnered after finishing my thesis nearly a decade ago.
I want to try and create a pre-emptive multitasking OS without any kernel mode software.
The basic idea for the initial PoC will be to have a tiny stub that runs on the A9 that sets the vector table to an unmapped address, maps some chunk of the on chip RAM and one AXI bus to the FPGA into virtual memory, then disables interrupts and drops to userspace.
At this point you're stuck in a padded cell, you've sandboxed yourself into user mode in a way that AFAIK you can never escape from.
So then you load a bitstream into the FPGA that contains an AXI bus master which, every X clock cycles, will send commands to the CoreSight APB bus to halt the A9, read out the register values and store them in block RAM, load a new saved context into the registers, and resume execution.
Essentially implementing pre-emptive multitasking from outside the CPU via CoreSight.
@poleguy@dlharmon As part of my thesis I already demonstrated an OS with no kernel-mode code, but it used a custom CPU that had a thread scheduler and other related functionality built into the RTL.
The logical extension, that I didn't finish because I wanted to graduate, was to see how close you can get to that idealized "no ring0 code at all" goal with silicon that's available for purchase COTS.
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