I really like the concept of FPGAs but when I want to actually get into them I remember that all the vendor bullshit and toolchain bullshit and HDL language design bullshit and I'm just way too tired to actually get through that and get into that ecosystem properly
@mei also like the entire toolchain is now a python package and you can manage & version it with the existing package manager on any OS instead of like, having to install native dependencies or whatever
@whitequark that does sound relevant. I'm definitely exhausted and sometimes people tell me I'm disabled but I mostly brush it off and pretend I'm fine and normal
what's the trade-off? can I use it to develop bitstreams for all/most FPGAs? (maybe with some compatibility step like transpiling through Verilog?) can I interact with hard IP?
amaranth brings python arithmetic semantics to FPGAs, and is itself written in python. so it assumes you're ok with python. note: it's not an "HLS" thing and it's not a "Python to FPGA compiler". it's just a way to construct netlists that's actually fit for purpose. it's very slightly lower level than verilog
> an I use it to develop bitstreams for all/most FPGAs?
@whitequark okay, this sounds very promising! one day I’ll give it a proper try…
amaranth brings python arithmetic semantics to FPGAs
hm, what do you mean? the biggest part of what comes to mind when i hear “python arithmetic semantics” is “everything’s a bigint”, which… surely not? i mean, you probably could do it with something like abstract interpretation but that doesn’t sound like the level of abstraction? the example on the playground actually does specify that count is 4 bits (which is good! but it means that I don’t understand what you mean here)
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