Trigger crossbar front panel board is back from fab.
It looks like I mostly pulled off the 0.5mm pitch BGA, but the Vbat via looks to be insufficiently tented so I might get it failing open there. Should have moved the via slightly further away from the ball to reduce the risk of such a failure.
Good news is, I don't think this will matter for two reasons.
The actual Vbat ball is not the one next to the via, it's the one to the right. The outer-ring ball is an unused GPIO that I'm just using as a route-through. The same is true of the via in the northeast corner of the array where the annular ring is eating into the BGA land.
In both cases the outer-ring ball is a route-through and so some wicking resulting in the BGA failing open at that pin won't matter whatsoever.
I'm not using the backup-memory feature anyway, and when Vdd is supplied the MCU runs off that instead.
@azonenberg I understand, it's not relevant to this design, and I don't know exactly what chip you are using here, but... wouldn't vbat leak via that unused GPIO? (assuming, e.g. VDDIO, if there is such a thing, being zero when powered off, and the battery then feeding into the io-structure)
@vogelchr It's a STM32L4 and that's a good question, I'm not sure if it would back-power the die. I guess we'll find out!
In this case there's no actual battery but Vbat is run by 3V3_SB (powered any time the device is plugged in) and Vdd is run by 3V3 (which is powered only when the device is in the "on" state). I did it this way in case I wanted to preserve any state across warm reboots, but at this time I have no immediate plans to use the feature for anything.
Worst case the 3V3_SB rail has enough current handling capacity that if I end up partially back-powering the MCU it won't hurt anything.
@azonenberg Assuming it's STM32L431xx in UFBGA100, the "bridging" GPIO is actually PC15, which has footnotes in the datasheet indicating that it belongs to the "backup power domain".
So, in case one would really use "Vbat" for the purpose that gave it its name it seems one would be safe.
Bug then again, when using it for a RTC, that GPIO would be consumed by the 32k-crystal 🤷♂️ ...
@azonenberg what did you use as via drill size? It always seems like the OSHPark boards have larger via holes than what I get from JLC with the same gerbers.
@adistuder My cad files had 250 μm finished hole size specified.
The minimum drill size on the website is 10 mils which is 254 μm but I round my design rules to round sizes in SI units (so I use 125 rather than 127 μm trace/space etc).
@adistuder I'll probably section one of these boards later on and get some actual dimensions of traces and such, maybe also sand down some soldermask and measure actual hole diameter and via wall thickness.
Checking actual as-manufactured dimensions of the BGA lands, they're slightly undersized (which aligns with my typical experience of smaller isolated copper features on OSHPark).
The elongated outer-ring pads are nominally 285 x 200 μm and measure closer to 250 x 167 μm.
The round inner-ring pads are nominally 285 μm diameter and measure 246 μm
So a bit on the small side compared to the design values, but not overetched to the point that I'm super worried about the board not working.
@tedyapo Focal plane is at the top of the profile.
Maybe I'll section one of these boards later on, I only need one of the three and this could be a nice test subject since it has a lot of skinny tracks.
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