@mcc As an alternative you can build your own inspection/tracing tooling (either using their JTAG blocks to make it accessible via JTAG, or via a SPI interface or the like).
It's work upfront, but it can be fun if you like enjoy work and it has the upside that you can take it with you to other FPGA toolchains.
I've used SPI for this more recently since the Lattice parts I've worked with are programmed that way, so already have a transport.
I think this is going to be the third or maybe fourth time I've learned to use Quartus SignalTap but none of them have taken. Maybe if I use SignalTap to solve an actual problem instead of running a toy scenario just to "learn to use SignalTap" it will actually stick
It is going bad. Despite me having used this before, on bringing up the SignalTap window it shows a yellow box reading "Invalid JTAG Configuration". Hm, I think. I should perform all configuration steps from the beginning. I bring up the documentation. I immediately find that the documentation's example demonstrating what you should expect the SignalTap window to look like contains the yellow box reading "Invalid JTAG Configuration".
It turns out "Invalid JTAG Configuration" in this case meant "You have to open the programmer dialog and say 'Run'". The SignalTap window will kick off a compilation for you but then it won't deploy it for you, I guess. I wasted an hour and a half trying to figure this out, during which time Quartus crashed twice.
Now I can boot it, and discover SignalTap simply doesn't support hi-dpi screens on Linux. These boxes can't be enlarged. Altera charges thousands of dollars for this application.
@slyecho So first off I'm discussing FPGAs specifically. And if you're discussing ASICs, whether they are able to tolerate an unstable clock depends on what is receiving the clock
@mcc@hazelweakly just be sure to mark it appropriately as such in constraints and give consideration as to how resets affect it and youll be probably fine good luck have fun
@violator@hazelweakly oh, i spent like, a couple months earlier this year attempting to create a clock constraints/SDC file that Quartus would actually accept. I never succeeded.
@mcc you can abuse clock wizards to do that as well, might make the constraints a bit simpler to write at the cost of complicating your signal path and hierarchy. Not that im recommending that path
@violator if there were a wizard for creating the sdc file I'd probably use it, especially if Intel would actually document it the way they don't seem to want to do with their TCL interfaces. Or do you mean make a PLL and then modify the files by hand
@mcc i always did the latter. Im fairly confident quartus has a clocking constraints wizard, but it was at least five years ago i last touched that wizard. Libero has one as well, used it more recently. Dont know about vivado, always just manually wrote those
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