“A hell of an improvement especially for the AMD EPYC servers”
Look closely at the stats in the headers of those three tables of test results. The NICs have different line speeds and the L3 cache sizes are different too. IPv4 and 6 for one and only IPv6 for the other.
This isn’t a benchmark of those systems, it’s showing that the code didn’t regress on either hardware set with some anecdotal data. It makes sense they’re not like for like.
Each table contains one column with the patches and one column without the patches - the hardware is unchanged. The different tables are to measure the impact of the patches across different hardware.
Reordering members can lead to better packing and a smaller memory footprint, due to how alignment works. If you’re iterating a large number of objects, having smaller objects is very favorable in terms of cache locality; you get fewer cache misses, and prefetching is more effective.
For the curious: pahole is a very useful tool for this type of code analysis.
Add comment