On Saturday 14th May, RISC-V celebrated its 14th birthday.
In recent years, the RISC-V community has grown from a small team to thousands of members spanning 70 countries. RISC-V is also in over 13 billion devices in the market, across multiple industries and sectors.
To learn more about Codethink's work with RISC-V, access our blog post about the RISC-V kernel testing pipeline.
Bought another #RISCV Milk-V Duo S for Apache #NuttX RTOS Release Testing ... Something strangely satisfying about NuttX on RISC-V: We finished the port in only 10 days! 👍
How do I call a RISC-V function? How do I jump? When and how should I save registers on the stack? What's the calling convention? How about the RISC-V ABI? Learn all this and more in my latest #riscv assembler post: https://projectf.io/posts/riscv-jump-function/
Google removes Android Generic Kernel Image support for RISC-V architecture, which means it'll be a lot tougher for device makers who want to port Android to RISC-V hardware moving forward, although Google says it's not ending RISC-V support altogether. https://buff.ly/4dhodf3#Android#RISCV#Google
「 Arm may be set up for a good decade long run in the datacenter, at the edge, and in our client devices, but watch out for RISC-V. Ten years from now, we might be writing the same story all over again, with one more historical ring wave added. In fact, it is hard to imagine any other alternative on the horizon 」
With all the valid concern around #llm and #genai power and water usage, I thought I'd start a blog series on tiny LLMs. Let's see what they can do on real tasks on very power efficient hardware.
Wish there was a decent "kickstarter* / #groupbuy for getting one of the many truly libre #riscv cores made by a #fab. Ideally one that is as much "general purpose cpu" as possible, though I can certainly do without out of order, speculative, and all the other fancy common sources of cpu vulnerabilities. It doesn't need to win speed records, just being really rock-solid would be awesome sigh