lupyuen, to random
@lupyuen@qoto.org avatar

Sophgo SG2000 SoC: A fascinating mix of 64-bit Cores (Arm too)

Source: https://github.com/lupyuen/nuttx-sg2000

lupyuen, to random
@lupyuen@qoto.org avatar

Bought another #RISCV Milk-V Duo S for Apache #NuttX RTOS Release Testing ... Something strangely satisfying about NuttX on RISC-V: We finished the port in only 10 days! 👍

Source: https://github.com/lupyuen/nuttx-sg2000

WillFlux, to random
@WillFlux@mastodon.social avatar

How do I call a RISC-V function? How do I jump? When and how should I save registers on the stack? What's the calling convention? How about the RISC-V ABI? Learn all this and more in my latest assembler post: https://projectf.io/posts/riscv-jump-function/

lupyuen, to linux
@lupyuen@qoto.org avatar

New release of Debian #Linux for #RISCV Sophgo SG200x / Milk-V Duo S ... Supports U-Boot "saveenv" 👍

Source: https://github.com/Fishwaldo/sophgo-sg200x-debian/releases/tag/v1.2.0

ekaitz_zarraga, to guix
@ekaitz_zarraga@mastodon.social avatar

Today in the journey: the gap between TinyCC and GCC is closing.

mentioned, too.

https://ekaitz.elenq.tech/bootstrapGcc13.html

lupyuen, to random
@lupyuen@qoto.org avatar
bradlinder, to android
@bradlinder@fosstodon.org avatar

Google removes Android Generic Kernel Image support for RISC-V architecture, which means it'll be a lot tougher for device makers who want to port Android to RISC-V hardware moving forward, although Google says it's not ending RISC-V support altogether. https://buff.ly/4dhodf3

jbzfn, to retrocomputing
@jbzfn@mastodon.social avatar

⚡Arm Is The New RISC/Unix, RISC-V Is The New Arm

「 Arm may be set up for a good decade long run in the datacenter, at the edge, and in our client devices, but watch out for RISC-V. Ten years from now, we might be writing the same story all over again, with one more historical ring wave added. In fact, it is hard to imagine any other alternative on the horizon 」

https://www.nextplatform.com/2022/09/22/arm-is-the-new-risc-unix-risc-v-is-the-new-arm/

kleaders, to llm
@kleaders@fosstodon.org avatar

With all the valid concern around and power and water usage, I thought I'd start a blog series on tiny LLMs. Let's see what they can do on real tasks on very power efficient hardware.

https://kyle.works/blog/tiny-llm-reviews-intro/

lupyuen, to random
@lupyuen@qoto.org avatar
lpwaterhouse, to random
@lpwaterhouse@ioc.exchange avatar

Wish there was a decent "kickstarter* / for getting one of the many truly libre cores made by a . Ideally one that is as much "general purpose cpu" as possible, though I can certainly do without out of order, speculative, and all the other fancy common sources of cpu vulnerabilities. It doesn't need to win speed records, just being really rock-solid would be awesome sigh

Fishwaldo, to milkv
@Fishwaldo@fosstodon.org avatar

Just updated my Debian images for MilkV DuoS support.
Many thanks @tllim and for giving me a DuoS board to get this done.

Grab the images here: https://github.com/Fishwaldo/sophgo-sg200x-debian

9to5linux, to RaspberryPi
@9to5linux@floss.social avatar
chiefgyk3d, to Cybersecurity
@chiefgyk3d@social.chiefgyk3d.com avatar

I wish I could justify spending a few hundred on this device as it looks really cool to tinker with my security in my lab.

https://www.crowdsupply.com/sutajio-kosagi/precursor

grahamperrin, to FreeBSD
@grahamperrin@bsd.cafe avatar

FreeBSD OpenJDK Contract

Various contracts, full- and part-time:

— bhyve hypervisor kernel improvements
— desktop usability
— developer tools such as LLD
— hardware support on new ARM and RISC-V devices
— installer
— jails – usability/orchestration/OCI-compatibility
— networking
— packaging – including package base (pkgbase)
— …

<https://freebsdfoundation.org/open-positions/>

@FreeBSDFoundation

lupyuen, to random
@lupyuen@qoto.org avatar

#PineVox Smart Speaker @PINE64 with 64-bit #RISCV BL606P ... Let's boot some Apache #NuttX RTOS! 👍

Source: https://github.com/lupyuen/nuttx-pinevox

jarkko, to RaspberryPi
@jarkko@social.kernel.org avatar

No more fighting with a loose TTL-USB-cables: I have USB hub shield with USB-to-UART port :-) Or two of these: one for Raspberry Pi 3B+ and other for VisionFive 2 RISC-V SBC (in the pic). Need to still pile a TPM2 chip to the pins on top of the shield and hopefully it will still work.

lovisix, to FreeBSD French
@lovisix@social.zdx.fr avatar

Ah purée, j'ai mis sur mon . Quelle machine !

Je suis à deux doigts de revendre mon X280 de 2019 pour ne garder que le X220 de 2011.

Il y a bien longtemps que l'informatique ne m'avais pas excité à ce point. Je crois que seul un portable avec pourrait atteindre ce plaisir de jouer.

Je parle d'un vrai portable, avec batterie amovible, port Ethernet, USB SD_Card Mini et Micro, switch physique pour le wifi et cache physique pour la caméra (ce qui manque au X220)

nmeum, to haskell
@nmeum@chaos.social avatar

Here is a preprint of fun paper that I've been working on which investigates the utilization of formal descriptions of instruction semantics to perform symbolic binary-level program analysis: https://doi.org/10.48550/arXiv.2404.04132

It includes a prototype implementation in Haskell which performs symbolic execution of RISC-V binary code without requiring the transformation to an intermediate representation (like LLVM IR).

pleia2, to random
@pleia2@floss.social avatar
scott, to GraphicsProgramming
@scott@denizens.social avatar
bsletten, to technology
@bsletten@mastodon.social avatar

This is huge. I’ve been bullish on RISC-V from the beginning but this is happening even faster than I expected. Between IT Sovereignty and geopolitics involving access to global supply chains, hyperspecialization of algorithms to hw, etc., it’s about to get really interesting.*

We’re one generation from the tech hacking culture of cyberpunk fiction.

  • HW heterogeneity will be mediated by LLVM and WebAssembly.

https://www.tomshardware.com/pc-components/cpus/former-silicon-valley-vets-create-risc-v-microprocessor-that-can-run-cpu-gpu-and-npu-workloads-simultaneously

winterschon, to embedded
@winterschon@hachyderm.io avatar

ohhhh gosh… more RISC-V for FreeBSD!

💘 more cores 💘 more ram 💘 more ports 💘 more more more 💘

going to validate whether this SO-DIMM format will work in my TuringPi2, but generally underlying all technical plans, a vast majority of my home-lab acquisitions are solely because I want it and it's fun!

💖👩🏼‍💻💁🏼‍♀️🤩😌

Lichee Pi 4A - front of retail box
Lichee Pi 4A - SoM and carrier board
Lichee Pi 4A - system layout

joeyh, to random
@joeyh@hachyderm.io avatar

Noticed that Jian Tan modified several additional test files besides those used in the known backdoor.

This was at the same time as the known backdoored test files, so almost certainly these RISC-V test files also contain a version of the backdoor. Used where I wonder?

ekaitz_zarraga, to guix
@ekaitz_zarraga@mastodon.social avatar

So today is time to publish another post about our effort for in and

Today I talk about being sidetracked and why that happened, so you can understand how many different projects are involved in the process, not only the compilers, and how all that works together:

https://ekaitz.elenq.tech/bootstrapGcc11.html

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