#lisp#CommonLisp#gopher#vhdl
I talk about the trivial basis for this month on a microcode implementation for @amszmidt 's #CADR4 lisp machine in vhdl using a mixture of lisp and Reichenbacher. links v
Time for my #introduction to the Fediverse! :masto_love:
Clash is an open source functional hardware description language built on #Haskell.
The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your #FPGA and #ASIC designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output #VHDL / #Verilog / #SystemVerilog code for synthesis.
The first part would be a UART with a small debugging interface that can read/write to memory. The CADR is entirely MMIO. Second step would be the CADR, and last all the peripherals (keyboard, frame buffer, ...). I think I should be able to do most of the work given the basic help and scaffolding ...
Have you fine Mastodon folks seen this awesome work?
First ever raytraced game thats not software? 1080p realtime, interactive, fixed+float point, 3D vector math, no CPU, no instructions, autopipelined in #FPGA! @suarezvictor's fantastic work w/ CflexHDL + PipelineC! #raytracing#graphics#hardware#gamedev#hdl#verilog#vhdl#eda