On Saturday 14th May, RISC-V celebrated its 14th birthday.
In recent years, the RISC-V community has grown from a small team to thousands of members spanning 70 countries. RISC-V is also in over 13 billion devices in the market, across multiple industries and sectors.
To learn more about Codethink's work with RISC-V, access our blog post about the RISC-V kernel testing pipeline.
Bought another #RISCV Milk-V Duo S for Apache #NuttX RTOS Release Testing ... Something strangely satisfying about NuttX on RISC-V: We finished the port in only 10 days! 👍
How do I call a RISC-V function? How do I jump? When and how should I save registers on the stack? What's the calling convention? How about the RISC-V ABI? Learn all this and more in my latest #riscv assembler post: https://projectf.io/posts/riscv-jump-function/
Google removes Android Generic Kernel Image support for RISC-V architecture, which means it'll be a lot tougher for device makers who want to port Android to RISC-V hardware moving forward, although Google says it's not ending RISC-V support altogether. https://buff.ly/4dhodf3#Android#RISCV#Google
「 Arm may be set up for a good decade long run in the datacenter, at the edge, and in our client devices, but watch out for RISC-V. Ten years from now, we might be writing the same story all over again, with one more historical ring wave added. In fact, it is hard to imagine any other alternative on the horizon 」
With all the valid concern around #llm and #genai power and water usage, I thought I'd start a blog series on tiny LLMs. Let's see what they can do on real tasks on very power efficient hardware.
— bhyve hypervisor kernel improvements
— desktop usability
— developer tools such as LLD
— hardware support on new ARM and RISC-V devices
— installer
— jails – usability/orchestration/OCI-compatibility
— networking
— packaging – including package base (pkgbase)
— …
No more fighting with a loose TTL-USB-cables: I have USB hub shield with USB-to-UART port :-) Or two of these: one for Raspberry Pi 3B+ and other for VisionFive 2 RISC-V SBC (in the pic). Need to still pile a TPM2 chip to the pins on top of the shield and hopefully it will still work. #arm#riscv#visionfive2#raspberrypi
Ah purée, j'ai mis #GhostBSD sur mon #X220. Quelle machine !
Je suis à deux doigts de revendre mon X280 de 2019 pour ne garder que le X220 de 2011.
Il y a bien longtemps que l'informatique ne m'avais pas excité à ce point. Je crois que seul un portable #RISCV avec #FreeBSD pourrait atteindre ce plaisir de jouer.
Je parle d'un vrai portable, avec batterie amovible, port Ethernet, USB SD_Card Mini et Micro, switch physique pour le wifi et cache physique pour la caméra (ce qui manque au X220)
Here is a preprint of fun paper that I've been working on which investigates the utilization of formal descriptions of instruction semantics to perform symbolic binary-level program analysis: https://doi.org/10.48550/arXiv.2404.04132
It includes a prototype implementation in Haskell which performs symbolic execution of RISC-V binary code without requiring the transformation to an intermediate representation (like LLVM IR).
This is huge. I’ve been bullish on RISC-V from the beginning but this is happening even faster than I expected. Between IT Sovereignty and geopolitics involving access to global supply chains, hyperspecialization of algorithms to hw, etc., it’s about to get really interesting.*
We’re one generation from the tech hacking culture of cyberpunk fiction.
HW heterogeneity will be mediated by LLVM and WebAssembly.