I think a lot of people undervalue RISC-V being a vendor neutral processor ISA, so I want to share the time when Intel retroactively standardized undocumented CPU features and made millions of third-party CPUs unable to run newer versions of Linux: https://www.jookia.org/wiki/Nopl
Ever played factorio and thought "I wish my factory had a risc-v core"?
Introducing Factorio Yosys!
This is a project of a friend of mine not on mastodon, so all credit to him. He built a full @yosyshq backend for #factorio that can now compile a #riscv core.
The core runs at 1.82 Hz at 60 FPS, and much faster with uncapped framerate.
Testing out this tiny little guy currently—RISC-V in a cute little cyberdeck package. What do you want to know about it? I'll work on a video soon! #riscv#cyberdeck#laptop (Disclosure: This laptop was provided for review by Sipeed)
Another Week - Another new image for #pinetabv (and #star64) - Kernel Version Bumps, Package Bumps in this release. Also, last actual release for PtV for a while, as now the images can be upgraded via "apt upgrade" online.
Major Changes for PtV include sound (enable it in settings), a updated kernel version 5.15.127 with the latest Starfive Vendor patches, improved EMMC performance, and a few thousand additional packages available via apt!
⚡ Firm headed by legendary chip architect behind AMD Zen finally releases first hardware — days after being selected to build the future of AI in Japan, Tenstorrent unveils Grayskull, its RISC-V answer to GPUs
「 Tenstorrent processors comprise a grid of cores known as Tensix Cores and come with network communication hardware so they can talk with one another directly over networks, instead of through DRAM 」
The binary that we have built is self-hosting and can build itself, though perhaps a few more bugfixes will be needed to reach the newest version of tcc.
This took quite a while again and I had needed some breaks here and there. Go 1.21RC2 has the necessary alignment checks for this to work without too much performance penalty otherwise caused if Linux or (even worse!) oreboot handled this.
In other news, this is a vast improvement to what OpenSBI offers. Less hacks, a cleaner architecture, and IT WORKS! 🥳
Does anyone understand #riscv traps and interrupts?
On interrupt I set mstatus.mpie to mstatus.mie and clear mstatus.mie to disable interrupts in the handler. Then mret copies the flag back again. That’s all fine and makes sense.
Trap entry (e.g. ebreak or illegal instruction) currently does the same, is that correct? If so how do I recover from a breakpoint in an interrupt handler? There’s only one level of prior interrupt enable so the enable gets lost.