Here is a preprint of fun paper that I've been working on which investigates the utilization of formal descriptions of instruction semantics to perform symbolic binary-level program analysis: https://doi.org/10.48550/arXiv.2404.04132
It includes a prototype implementation in Haskell which performs symbolic execution of RISC-V binary code without requiring the transformation to an intermediate representation (like LLVM IR).
This is huge. I’ve been bullish on RISC-V from the beginning but this is happening even faster than I expected. Between IT Sovereignty and geopolitics involving access to global supply chains, hyperspecialization of algorithms to hw, etc., it’s about to get really interesting.*
We’re one generation from the tech hacking culture of cyberpunk fiction.
HW heterogeneity will be mediated by LLVM and WebAssembly.
💘 more cores 💘 more ram 💘 more ports 💘 more more more 💘
going to validate whether this SO-DIMM format will work in my TuringPi2, but generally underlying all technical plans, a vast majority of my home-lab acquisitions are solely because I want it and it's fun!
Noticed that Jian Tan modified several additional test files besides those used in the known #xz backdoor.
This was at the same time as the known backdoored test files, so almost certainly these RISC-V test files also contain a version of the backdoor. Used where I wonder?
Today I talk about being sidetracked and why that happened, so you can understand how many different projects are involved in the process, not only the compilers, and how all that works together:
🤖 Duo S RISC-V/Arm SBC features Sophgo SG2000 SoC, Ethernet, WiFi 6, and Bluetooth 5 connectivity - CNX Software
「 Linux and RTOS are said to be supported on the Duo S, and you’ll find buildroot-built OS images on GitHub to boot from either the microSD card or the eMMC flash. As of the current v1.0.9 image, Duo S does not yet support wiringX (C) and pinpong (Python) GPIO libraries, and Arduino support is not implemented either 」
🔐 Linux 6.9 Adds New RISC-V Vector-Accelerated Crypto Routines - Phoronix
「 RISC-V with Linux 6.9 implements support for more vector-accelerated crypto routines. Among the work is RISC-V vector accelerated AES-{ECB,CBC,CTR,XTS}, ChaCha20, GHASH, SHA-256, SHA-384, SHA-512, SM3, and SM4 algorithms 」
⚡ Firm headed by legendary chip architect behind AMD Zen finally releases first hardware — days after being selected to build the future of AI in Japan, Tenstorrent unveils Grayskull, its RISC-V answer to GPUs
「 Tenstorrent processors comprise a grid of cores known as Tensix Cores and come with network communication hardware so they can talk with one another directly over networks, instead of through DRAM 」
Testing out this tiny little guy currently—RISC-V in a cute little cyberdeck package. What do you want to know about it? I'll work on a video soon! #riscv#cyberdeck#laptop (Disclosure: This laptop was provided for review by Sipeed)
If anyone has interest or questions about the #bootstrapping process, feel free to ask. I think I should talk more about this, and share what we do and how, because it's really interesting.
For example, this week I implemented many pseudoinstructions for the #RISCV backend in #tinycc and added some extended assembly support.
Banning China from accessing advanced silicon meant only one thing: that China is now at the frontline of innovation on an open architecture like #RiscV, while America is throwing its money at a dead body like #Intel.
Bit of frustration tonight making VisionFive 2 builds of #HaikuOS . Mine kept hanging at MMCBusDriver. Thankfully X512 ‘s January build (just dumped with dd on the NVMe) boots fine. Mouse isn’t working though so I can just look at it I guess 😅
Succeeded in getting the guix system vm to support --target=riscv64-linux-gnu, and --system=riscv64-linux(but not quite)
The qemu running with --system=riscv64-linux is also riscv architecture, now you have to manually modify to use native qemu or the guix of QEMU-system on qemu-user is too slow
#RISCV "Wait for Interrupt instruction (WFI) provides a hint to the implementation that the current hart can be stalled until an interrupt ... so a legal implementation is to simply implement WFI as a NOP" 🤔
I am happy to announce the 1.1.0 release of Mecrisp-Quintus, an optimising #Forth compiler capable of generating native code with constant folding and register allocation which is now also available for 64 bit #riscv RV64IM and RV64IMC targets in addition to RV32I(M)(C) and MIPS M4K.
The #tiktokban starts to look bad when it comes to accessing any tech, all the sudden your successful little GitHub repo requires a lawyer with ties to the intelligence community.
They're trying to ruin #RISCV, they already successfully managed to slow China access to the latest semiconductor tech, but YOU could be next if they decide to put you on the same list for not supporting bombing a daycare center.
I don't fear the #CCP, I fear US lawmakers drawing invisible lines for the rest of us.
Ever played factorio and thought "I wish my factory had a risc-v core"?
Introducing Factorio Yosys!
This is a project of a friend of mine not on mastodon, so all credit to him. He built a full @yosyshq backend for #factorio that can now compile a #riscv core.
The core runs at 1.82 Hz at 60 FPS, and much faster with uncapped framerate.
Fooling around with the VisionFive 2 again, this time trying to get a reasonable xrdp experience going so I can use it from my Mac and Windows PCs without switching display and inputs. I would probably use it much more frequently if I could do so from the main machines I work on.
So far, I've gotten an xfce4 session working in which I have reasonable performance but can't get any app windows to appear, or a GNOME session that works fine but with about a 30-second lag.
i hope #zig will be sustainable. i like its way more than #rust. and like in C or even RISC-V microarchitecture, but not so much in Rust and C++, the language definition is compact enough so that it just stick into your head. also, comptime is really cool invention in my opinion. #C#rustlang#riscv